IIC bus start-stop detection circuit
AssigneeSTMicroelectronics Asia Pacific Pte Ltd
InventorsNee Loong Wilson Low, Chaochao Zhang
Life of this patent
Estimating the term…
Abstract
A start/stop condition detection circuit is coupled to receive the SDA and SCL signals from an IIC Bus. The circuit generates a first signal in response to an edge of the SDA signal and generates an inversion of the first signal as a second signal in response to an opposite edge of the SCL signal. The first and second signals are logically combined to generate an output signal. The particular directions of the edges of the SDA and SCL signals that the circuit is response to determines whether the output signal is indicative of a start condition detection or a stop condition detection.
Claims26
A circuit, comprising:
- a first input configured to receive an SDA signal;
- a second input configured to receive an SCL signal;
- a first logic circuit configured to generate a first signal having a first logic state in response to a rising edge of the SCL signal;
- a second logic circuit configured to invert the first signal and generate a second signal having a second logic state in response to a falling edge of the SDA signal;
- and
- a third logic circuit operable responsive to the first logic state of the first signal and second logic state of the second signal to generate a start signal indicative of a start condition on a bus comprising the SDA and SCL signals.
A circuit, comprising:
- a first input configured to receive an SDA signal;
- a second input configured to receive an SCL signal;
- a first logic circuit configured to generate a first signal having a first logic state in response to a falling edge of the SCL signal;
- a second logic circuit configured to invert the first signal and generate a second signal having a second logic state in response to a rising edge of the SDA signal;
- and
- a third logic circuit operable responsive to the first logic state of the first signal and second logic state of the second signal to generate a stop signal indicative of a stop condition on a bus comprising the SDA and SCL signals.
A circuit, comprising:
- a first input configured to receive an SDA signal;
- a second input configured to receive an SCL signal;
- a first circuit configured to sense a rising edge of the SCL signal and generate a first signal;
- a second circuit configured to sense a falling edge of the SDA signal and pass an inversion of the first signal as a second signal;
- and
- a logic circuit configured to logically combine the first and second signals to generate a start condition signal for a bus comprising the SDA and SCL signals.
A circuit, comprising:
- a first input configured to receive an SDA signal;
- a second input configured to receive an SCL signal;
- a first circuit configured to sense a falling edge of the SCL signal and generate a first signal;
- a second circuit configured to sense a rising edge of the SDA signal and pass an inversion of the first signal as a second signal;
- and
- a logic circuit configured to logically combine the first and second signals to generate a stop condition signal for a bus comprising the SDA and SCL signals.
A circuit, comprising:
- a first input configured to receive an SDA signal;
- a second input configured to receive an SCL signal;
- a start/stop condition detection circuit coupled to receive the SDA and SCL signals and configured to:
- generate a first signal in response to an edge of the SDA signal;
- generate an inversion of the first signal as a second signal in response to an opposite edge of the SCL signal;
- and
- logically combine the first and second signals to generate an output signal indicative of start/stop condition detection.
Dependencies are inferred from the claim text.