US 9,436,632 B2 · Accessing data stored in a command/address register device

Abstract

A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

Claims20

Dependent claims

An apparatus comprising:

a dynamic random access memory (DRAM) comprising at least one page having at least one multipurpose register (MPR) and comprising:
a first interface that, when operatively coupled to an address bus, is to receive a control word (CW) and provide the CW to a particular MPR and
a second interface communicatively coupled to the at least one page having at least one MPR, wherein:
the at least one page having at least one MPR to be written-to using the first interface during a coupling of the first interface to the address bus and to be read-from using the second interface during a coupling of the second interface to a data bus.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

14/560,976Filed 4 Dec 2014 · continuation

Published

US 2015/0089111 A126 Mar 2015

Granted

6 Sep 2016

Term ends

Not estimatedThe source records don’t support an estimate.

Classification15 codes

G11C 7/1072
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: for memories with random access ports…
G06F 11/073
The processing taking place on a specific hardware platform or in a specific software environment: in a memory management context, e.g. virtual…
G06F 11/0787
Error or fault reporting or storing: storage of error reports, e.g. persistent data storage, storage using memory protection
G06F 11/10
Error detection or correction by redundancy in data representation, e.g. by using checking codes: adding special bits or symbols to the coded…

Family

PCT/US2011/066891Parent of this continuation · filed 22 Dec 2011

US 2015/0089111 A1Pre-grant publication · published 26 Mar 2015

Application13/995,477Parent of this continuation

US 2014/0372816 A1Published application

US 9,442,871 B2Related patent

US 9,436,632 B2This patent

From the US filing history. Foreign family members aren’t listed.

Accessing data stored in a command/address register device

Life of this patent

Accessing data stored in a command/address register device

Life of this patent

Abstract

Claims20