Back to results
US 9,436,631 B2Granted
Chip including memory element storing higher level memory data on a page by page basis
AssigneePact Xpp Technologies AG
InventorMartin Vorbach
Life of this patent
Estimating the term…
Abstract
A bus system for transferring data between parts of a multiprocessor system. The bus system is divided into a plurality of segments. Each segment is controlled by a table providing routing information. The bus system establishes communication between a sender and a receiver according to data where the data includes an identifier that identifying the source of the data transfer and/or the target of the data transfer.
Claims14
A bus system for transferring data between parts of a multiprocessor system, the bus system comprising:
- a plurality of bus segments for each processor of the multiprocessor system comprising a plurality of flexible data channels to each processor of the multiprocessor system according to algorithms to be executed, wherein a plurality of algorithms may executed in parallel;
- wherein a communication between a sender and a receiver is established in accordance with a data transfer for an executed algorithm;
- and
- at least one identifier is transmitted with the data for at least one of:
- identifying a source of the data transfer;
- and selecting a target of the data transfer.
3 more elements
A bus system for transferring data between parts of a multiprocessor system, the bus system comprising:
- a plurality of bus segments for each processor of the multiprocessor system comprising a plurality of flexible data channels to each processor of the multiprocessor system;
- wherein a communication between a sender and a receiver is established in accordance with a data transfer;
- and
- at least one identifier is transmitted with the data for at least one of:
- identifying a source of the data transfer;
- and selecting a target of the data transfer.
3 more elements
Dependencies are inferred from the claim text.