US 9,436,630 B2 · Using dual phys to support multiple PCIe link widths

Abstract

Systems described herein enable PCIe device components to be used with multiple PCIe topologies and with host systems of varying configurations. In some cases, a number of varying PHYs and PCIe cores are utilized to increase the number of applications and/or specifications that may be satisfied with a host interface design. Further, some systems described herein may include a number of synchronizers, clock multiplier units, and selectors to create a host interface that can be configured for a number of applications. Despite increasing the flexibility of the usage of systems disclosed herein, costs can be reduced by using the systems of the present disclosure for PCIe based devices.

Claims28

Dependent claims

A storage device, comprising:

a plurality of non-volatile solid state memory devices;
a set of Peripheral Component Interconnect Express (PCIe) connectors configured to receive memory access commands from a host system;
and
a controller configured to receive and process memory access commands for accessing the plurality of non-volatile solid state memory devices, the controller comprising a host interface, the host interface comprising:
a plurality of physical interfaces (PHYs), each PHY configured to communicate with a subset of PCIe connectors from the set of PCIe connectors, wherein at least one of the plurality of PHYs comprises a dual PCIe PHY, thereby enabling the host interface to be used with multiple PCIe topologies;
and
one or more PCIe cores configured to process signals passing through the plurality of PHYs.

4 more elements

Dependencies are inferred from the claim text.

Using dual phys to support multiple PCIe link widths

Life of this patent

Using dual phys to support multiple PCIe link widths

Life of this patent

Abstract

Claims28