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US 9,436,619 B2Granted
Multi-level, hardware-enforced domain separation using a separation kernel on a multicore processor with a shared cache
AssigneeRaytheon Company
InventorBrandon Woolley
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Abstract
A separation kernel isolating memory domains within a shared system memory is executed on the cores of a multicore processor having hardware security enforcement for static virtual address mappings, to implement an efficient embedded multi-level security system. Shared caches are either disabled or constrained by the same static virtual address mappings using the hardware security enforcement available, to isolate domains accessible to select cores and reduce security risks from data co-mingling.
Claims20
An apparatus, comprising:
- a multicore processor including a plurality of processing cores, a plurality of memory management units, and a plurality of peripheral access management units, each of the processing cores configured to operate exclusively with only one of the memory management units and each of the processing cores configured to operate with one or more of the peripheral access management units;
- a first cache and a second cache each configured to be shared by at least two of the processing cores;
- and
- a separation kernel configured to execute within each of the plurality of processing cores, the separation kernel configured to enforce static virtual address mappings that form at least two isolated memory domains within a shared system memory and the first and second shared caches,
- wherein two or more of the processing cores including a first processing core and excluding a second processing core are configured to employ the first shared cache, and
- wherein two or more of the processing cores including the second processing core and excluding the first processing core are configured to employ the second shared cache.
3 more elements
An apparatus, comprising:
- a multicore processor including a plurality of processing cores, a plurality of memory management units, and a plurality of peripheral access management units, each of the processing cores configured to operate exclusively with only one of the memory management units and each of the processing cores configured to operate with one or more of the peripheral access management units;
- a first cache and a second cache each configured to be shared by at least two of the processing cores;
- and
- a separation kernel configured to execute within each of the plurality of processing cores, the separation kernel configured to enforce static virtual address mappings that form at least two isolated memory domains within a shared system memory and the first and second caches,
- wherein the apparatus is configured to isolate the at least two isolated memory domains by enforcing the static virtual address mappings such that:
- a first of the processing cores operates with one of the at least two isolated memory domains, and
- a second of the processing cores separately operates with another of the at least two isolated memory domains,
- wherein two or more of the processing cores including the first processing core and excluding the second processing core are configured to employ the first shared cache, and
- wherein two or more of the processing cores including the second processing core and excluding the first processing core are configured to employ the second shared cache.
6 more elements
A method, comprising:
- operating each of a plurality of processing cores within a multicore processor exclusively with only one of a plurality of memory management units and with one or more of a plurality of peripheral access management units;
- selectively sharing each of a first cache and a second cache by at least two of the processing cores;
- executing a separation kernel within each of the plurality of processing cores, the separation kernel configured to enforce static virtual address mappings that form at least two isolated domains within a shared system memory and the first and second shared caches;
- employing the first shared cache for two or more of the processing cores including a first processing core and excluding a second processing core;
- and
- employing the second shared cache for two or more of the processing cores including the second processing core and excluding the first processing core.
3 more elements
An apparatus, comprising:
- a multicore processor including a plurality of processing cores each associated with a memory management unit and one or more peripheral access management units, the memory management units and the peripheral access management units each configured to selectively enforce static virtual address mappings;
- a first cache and a second cache each shared by at least two of the processing cores;
- and
- a separation kernel configured to execute within each of the plurality of processing cores, the separation kernel configured to cause the memory management units and the peripheral access management units to enforce the static virtual address mappings to form at least two isolated memory domains within a shared system memory and the first and second shared caches,
- wherein the apparatus is configured to operate at least a first of the processing cores with a first of the at least two isolated memory domains exclusive of a second of the at least two isolated memory domains, and to separately operate at least a second of the processing cores with the second of the at least two isolated memory domains exclusive of the first of the at least two isolated memory domains,
- wherein two or more of the processing cores including the first processing core and excluding the second processing core are configured to employ the first shared cache, and
- wherein two or more of the processing cores including the second processing core and excluding the first processing core are configured to employ the second shared cache.
4 more elements
Dependencies are inferred from the claim text.