Processor, cache memory of the processor and control method of the processor
AssigneeNational Sun Yat-Sen University
InventorsIng-Jer Huang, Chun-Hung Lai
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Abstract
A processor capable of storing trace data is disclosed. The processor includes a core adapted to execute programs, as well as a cache memory electrically connected to the core. The cache memory includes a core way and a trace way. The core way is adapted to store data that is required when the core executes the programs. The trace way is adapted to store data that is generated during debugging operations of the core. A control method of the processor is also disclosed.
Claims21
A processor capable of storing trace data, comprising:
- a core adapted to execute programs;
- and
- a cache memory electrically connected to the core and comprising a core way and a trace way, wherein the core way is adapted to store data that is required when the core executes the programs, and wherein the trace way is adapted to store data that is generated during debugging operations of the core,
- wherein each of the core way and the trace way comprises a data memory, a tag memory and a write back address memory, wherein the data memory of the core way is adapted to store the data that is required when the core executes the programs, wherein the data memory of the trace way is adapted to store the data that is generated during the debugging operations of the core, wherein the tag memory stores a plurality of states of row and a plurality of tags, and selects one of the plurality of states of row and one of the plurality of tags according to an address outputted by the core, wherein the write back address memory is adapted to store a plurality of row addresses, wherein the cache memory further comprises:
- a data/trace cache control register adapted to store a predetermined trace address and a plurality of cache way control bits, wherein each of the plurality of cache way control bits corresponds to a respective one of the data memories and comprises two state values;
- a line index calculator generating a trace address, a trace data and a trace enabling bit according to the plurality of cache way control bits, a valid trace bit and the data that is generated during the debugging operations of the core;
- a cache controller generating a core data, a core enabling bit and a cache way cleaning bit according to the address outputted by the core and the data that is required when the core executes the programs, wherein the address comprises a set index and an address tag;
- a plurality of data/trace configuration units, each corresponding to a respective one of the plurality of cache way control bits, wherein each of the plurality of data/trace configuration units controls the core data to be written into the data memory according to one of the two state values of the cache way control bit, the set index and the core enabling bit, or controls the trace data to be written into the data memory according to another one of the two state values of the cache way control bit, the trace address and the trace enabling bit;
- a plurality of comparators, each comparing the address tag with the tag outputted by the tag memory and generating a tag hit bit;
- a plurality of trace protection units, each generating a locking bit and a hit bit according to a corresponding one of the plurality of cache way control bits, the plurality of states of row outputted by the tag memory and the tag hit bit;
- and
- a plurality of trace dump units, each generating a write-back address according to a corresponding one of the plurality of cache way control bits, the plurality of row addresses, the plurality of states of row and the predetermined trace address.
A cache memory of a processor capable of storing trace data, comprising:
- a core way;
- a trace way, wherein each of the core way and the trace way comprises a data memory, a tag memory and a write back address memory, wherein the data memories of the core way and the trace way are adapted to store data, wherein the tag memory stores a plurality of states of row and a plurality of tags, and selects one of the plurality of states of row and one of the plurality of tags according to an address outputted by the core, wherein the write back address memory is adapted to store a plurality of row addresses;
- a data/trace cache control register adapted to store a predetermined trace address and a plurality of cache way control bits, wherein each of the plurality of cache way control bits corresponds to a respective one of the data memories and comprises two state values;
- a line index calculator generating a trace address, a trace data and a trace enabling bit according to the plurality of cache way control bits, a valid trace bit and a data that is generated during the debugging operations of the core;
- a cache controller generating a core data, a core enabling bit and a cache way cleaning bit according to the address outputted by the core and a data that is required when the core executes programs, wherein the address comprises a set index and an address tag;
- a plurality of data/trace configuration units, each corresponding to a respective one of the plurality of cache way control bits, wherein each of the plurality of data/trace configuration units controls the core data to be written into the data memory according to one of the two state values of the cache way control bit, the set index and the core enabling bit, or controls the trace data to be written into the data memory according to another one of the two state values of the cache way control bit, the trace address and the trace enabling bit;
- a plurality of comparators, each comparing the address tag with the tag outputted by the tag memory and generating a tag hit bit;
- a plurality of trace protection units, each generating a locking bit and a hit bit according to a corresponding one of the plurality of cache way control bits, the plurality of states of row outputted by the tag memory and the tag hit bit;
- and
- a plurality of trace dump units, each generating a write-back address according to a corresponding one of the plurality of cache way control bits, the plurality of row addresses, the plurality of states of row and the predetermined trace address.
A control method of a processor capable of storing trace data, wherein the processor comprises a core and a cache memory, wherein the cache memory comprises a data/trace cache control register, a line index calculator, a cache controller, a plurality of data/trace configuration units, a plurality of comparators, a plurality of trace protection units, a plurality of trace dump units, a plurality of data memories, a plurality of tag memories and a plurality of write back address memories, wherein the data/trace cache control register is electrically connected to the line index calculator, the plurality of data/trace configuration units, the plurality of trace protection units and the plurality of trace dump units, wherein the plurality of data/trace configuration units is electrically connected to the line index calculator, the cache controller and the data memories, wherein the plurality of comparators is electrically connected to the plurality of trace protection units and the plurality of tag memories, wherein the plurality of tag memories is electrically connected to the plurality of trace protection units and the plurality of trace dump units, wherein the plurality of trace dump units is electrically connected to the plurality of write back address memories, the control method comprises:
- setting the data/trace cache control register by the core to operate one of the plurality of data memories, one of the plurality of tag memories and one of the plurality of write back address memories as one trace way;
- testing the core by a trace generation unit and retrieving an output signal of the core as a trace data;
- generating a storage address of the trace data by a line index calculator;
- writing the trace data into the data memory of the trace way according to the storage address by one of the plurality of data/trace configuration units;
- determining whether the data memory of the trace way is full by the data/trace configuration unit,
- updating the storage address by the line index calculator if the data memory of the trace way is not full, allowing the data memory of the trace way to store a further trace data;
- prohibiting the trace data from being written into the data memory of the trace way by the line index calculator if the data memory of the trace way is full;
- outputting the trace data stored in the data memory of the trace way;
- and
- cleaning the data memory of the trace way by the core.
Dependencies are inferred from the claim text.