System and method to defragment a memory

A system comprising:

• a memory comprising a plurality of physical memory addresses;
• a memory management unit (MMU) configured to store a page table associated with a virtual memory, the page table including lookup information associated with a first virtual memory address;
• and
• a data cache that includes a defragmentation circuit configured to perform a memory defragmentation operation comprising:
• loading data stored at a first physical memory address of the memory from the memory into a cache line of the data cache, wherein the first physical memory address is mapped to the first virtual memory address;
• initiating modification of the lookup information, wherein the modification of the lookup information remaps the first virtual memory address from the first physical memory address to a second physical memory address of the memory;
• and
• modifying information associated with the cache line to indicate that the cache line corresponds to the second physical memory address instead of the first physical memory address.

A non-transitory computer-readable medium comprising instructions that, when executed by a processor, cause the processor to perform operations comprising:

• loading data stored at a first physical memory address of a memory from the memory into a cache line of a data cache, wherein the first physical memory address is mapped to a first virtual memory address;
• initiating modification of lookup information stored in a page table, the page table associated with a virtual memory, the lookup information associated with the first virtual memory address, wherein the modification of the lookup information remaps the first virtual memory address from the first physical memory address to a second physical memory address of the memory;
• and
• modifying information associated with the cache line to indicate that the cache line corresponds to the second physical memory address instead of the first physical memory address.

A system comprising:

• means for storing data using a plurality of physical memory addresses;
• and
• means for caching data, wherein the means for caching the data includes a defragmentation circuit configured to:
• load data stored at a first physical memory address of a memory from the memory into a cache line of a data cache, wherein the first physical memory address is mapped to a first virtual memory address;
• initiate modification of lookup information stored in a page table, the page table associated with a virtual memory, the lookup information associated with the first virtual memory address, wherein the modification of the lookup information remaps the first virtual memory address from the first physical memory address to a second physical memory address of the memory;
• and
• modify information associated with the cache line to indicate that the cache line corresponds to the second physical memory address instead of the first physical memory address.