Semiconductor device with nonvolatile memory prevented from malfunctioning caused by momentary power interruption

A semiconductor device including a nonvolatile memory, comprising:

• an internal register storing a value for controlling an operation of said nonvolatile memory;
• a power shutoff detection register holding a value which changes when power shutoff occurs, configured of a latch circuit holding a value which is more prone to change than the value held in said internal register when power shutoff occurs and including a plurality of P-channel MOS transistors and a plurality of N-channel MOS transistors, configured so that a specific P-channel MOS transistor and a specific N-channel MOS transistor among said plurality of P-channel MOS transistors and said plurality of N-channel MOS transistors have a greater gate width than that of the other P-channel MOS transistor and the other N-channel MOS transistor to have an enhanced drive ability and accordingly a value held in the power shutoff detection register is more prone to change when power shutoff occurs;
• and
• a controller for controlling the operation of said nonvolatile memory in accordance with the value stored in said internal register, wherein said controller stops a data rewrite operation for said nonvolatile memory, when said controller detects power shutoff based on a change of the value held in said power shutoff detection register while said data rewrite operation is performed.

A semiconductor device including a processor and a nonvolatile memory, comprising:

• an internal register storing a value for controlling an operation of said nonvolatile memory;
• a power shutoff detection register holding a value which changes when power shutoff occurs, configured of a latch circuit holding a value which is more prone to change than the value held in said internal register when power shutoff occurs and including a plurality of P-channel MOS transistors and a plurality of N-channel MOS transistors, configured so that a specific P-channel MOS transistor and a specific N-channel MOS transistor among said plurality of P-channel MOS transistors and said plurality of N-channel MOS transistors have a greater gate width than that of the other P-channel MOS transistor and the other N-channel MOS transistor to have an enhanced drive ability and accordingly a value held in the power shutoff detection register is more prone to change when power shutoff occurs;
• and
• a controller for controlling the operation of said nonvolatile memory in accordance with the value stored in said internal register, wherein said controller stops a data rewrite operation for said nonvolatile memory, when said controller detects power shutoff based on a change of the value held in said power shutoff detection register while said data rewrite operation is performed, and notifying said processor of occurrence of the power shutoff.