Memory bit MBIST architecture for parallel master and slave execution
AssigneeAdvanced Micro Devices, Inc.
InventorsAtchyuth K Gorti, Archana Somachudan
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AssigneeAdvanced Micro Devices, Inc.
InventorsAtchyuth K Gorti, Archana Somachudan
Estimating the term…
A scalable, reconfigurable Memory Built-In Self-Test (MBIST) architecture for a semiconductor device, such as a multiprocessor, having a Master and one or more Slave MBIST controllers is described. The MBIST architecture includes a plurality of MBISTDP interfaces connected in a ring with the Master MBIST controller. Each MBISTDP interface connects to at least one Slave controller for forwarding test information streamed to it from the Master MBIST controller over the ring. Test information includes test data, address, and MBIST test commands. Each MBISTDP interface forwards the information to the Slave controller attached thereto and to the next MBISTDP interface on the ring. Test result data is sent back to the Master MBIST controller from the MBISTDP interfaces over the ring.
An apparatus having a built-in self-test (BIST) architecture comprising:
A method of conducting memory built-in self-test (MBIST) testing in a semiconductor device comprising:
A non-transitory computer-readable storage device encoded with data that, when implemented in a manufacturing facility, adapts the manufacturing facility to create an apparatus that, when operated, performs a process comprising:
Dependencies are inferred from the claim text.