Circuit network with an error detection system for mitigation of error propagation

An apparatus, comprising:

• a first network including:
• a first data bus and a second data bus;
• a first circuit coupled for communication via the first data bus;
• a first plurality of storage elements coupled to the first data bus and the second data bus;
• a second circuit coupled for communication via the second data bus;
• and
• an error detection system coupled to the first data bus and the second data bus;
• the error detection system configured to compare first data on the first data bus with corresponding second data on the second data bus;
• and
• the error detection system configured to generate an error signal responsive to mismatch between the first data and the second data;
• a second network including:
• a third data bus and a fourth data bus;
• a third circuit coupled for communication via the third data bus;
• a second plurality of storage elements coupled to the third data bus and the fourth data bus;
• and
• a fourth circuit coupled for communication via the fourth data bus;
• and
• a multiplexer coupled to receive first output data from the second circuit and second output data from the fourth circuit as respective sets of data inputs, and further coupled to receive the error signal as a control select signal to select either the first output data or the second output data as a multiplexer output.

A method, comprising:

• busing first data from a first circuit for communication via a first data bus to a plurality of storage elements and an error detection system coupled to the first data bus;
• busing second data from the plurality of storage elements for communication via a second data bus to the error detection system and a second circuit;
• determining a first parity of the first data by the error detection system;
• determining a second parity of the second data by the error detection system;
• comparing the first parity and the second parity by the error detection system;
• asserting an error signal responsive to a mismatch between the first parity and the second parity;
• providing the first data to both the plurality of storage elements and the error detection system via first routing nodes of the first data bus;
• providing the second data to both the error detection system and the second circuit via second routing nodes of the second data bus;
• the first routing nodes coupled nearer to the first circuit for a first routing pipeline coverage end of the error detection system as associated with the first data on the first data bus;
• and
• the second routing nodes coupled nearer to the second circuit for a second routing pipeline coverage end of the error detection system as associated with the second data on the second data bus.