Data storing method, memory control circuit unit and memory storage device

A data storing method for a rewritable non-volatile memory module comprising a plurality of physical erasing units, wherein each of the physical erasing units comprising a plurality of physical programming units, wherein each of the physical programming units comprises a data bit area and a redundancy bit area, and the data storing method comprising:

• establishing a parity address correspondence table;
• generating a parity according to first data;
• programming the first data into a first physical programming unit among the physical programming units;
• programming the parity into at least one second physical programming unit among the physical programming units;
• and
• recording at least one mark into the parity address correspondence table, wherein the at least one mark indicates that the parity is programmed into the at least one second physical programming unit.

A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units, each of the physical erasing units comprises a plurality of physical programming units, and each of the physical programming units comprises a data bit area and a redundancy bit area, the memory control circuit unit comprising:

• a host interface configured to couple to a host system;
• a memory interface configured to couple to the rewritable non-volatile memory module;
• and
• a memory management circuit coupled to the host interface and the memory interface,
• wherein the memory management circuit is configured to generate a parity according to first data,
• wherein the memory management circuit is further configured to program the first data into a first physical programming unit among the physical programming units,
• wherein the memory management circuit is further configured to program the parity into at least one second physical programming unit among the physical programming units, wherein the at least one second physical programming unit is arranged after the first physical programming unit,
• wherein in the operation of programming the first data into the first physical programming unit among the physical programming units, the memory management circuit programs at least one mark into the redundancy bit area of the first physical programming unit, wherein the at least one mark indicates that the parity is programmed into the at least one second physical programming unit.

A memory storage device, comprising:

• a connection interface unit configured to couple to a host system;
• a rewritable non-volatile memory module comprising a plurality of physical erasing units, wherein each of the physical erasing units comprises a plurality of physical programming units, and each of the physical programming units comprises a data bit area and a redundancy bit area;
• and
• a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module,
• wherein the memory control circuit unit is configured to generate a parity according to first data,
• wherein the memory control circuit unit is further configured to program the first data into first physical programming unit among the physical programming units,
• wherein the memory control circuit unit is further configured to program the parity into at least one second physical programming unit among the physical programming units, wherein the at least one second physical programming unit is arranged after the first physical programming unit,
• wherein in the operation of programming the first data into the first physical programming unit among the physical programming units, the memory control circuit unit programs at least one mark into the redundancy bit area of the first physical programming unit, wherein the at least one mark indicates that the parity is programmed into the at least one second physical programming unit.