Apparatus for error detection in memory devices

Apparatus for transfer of data elements between a bus master and a memory controller for a memory storage device, the apparatus comprising:

• an address translator arranged to receive a write address from the bus master, to modify the write address into a modified write address, and to send the modified write address to the memory controller,
• the address translator being further arranged to receive a read address from the bus master, to modify the read address into a modified read address, and to send the modified read address to the memory controller, and
• wherein the address translator is further arranged to modify the read or write address into the modified read or write address by multiplying a difference between the read or write address and a base address with an expansion factor K, where the expansion factor K is greater than one;
• an ECC calculator arranged to receive write input data associated with the write address from the bus master and to generate an error correction code on the basis of the write input data;
• a concatenator arranged to receive the write input data from the bus master, to receive the error correction code from the ECC calculator, to concatenate the write input data and the error correction code to obtain write output data, and to send the write output data to the memory controller;
• and
• a data checker arranged to receive read input data associated with the modified read address from the memory controller, wherein the read input data comprises a data element and an error correction code,
• the data checker being further arranged to correct the data element on the basis of the error correction code, to obtain a corrected data element, and to send the corrected data element to the bus master.