Semiconducotr memory device including non-volatile memory cell array

A semiconductor memory device, comprising:

• a dynamic random access memory (DRAM) cell array;
• a nonvolatile memory cell array configured to store input data and a first set of parity bits having at least one bit, the input data and the first set of parity bits received from outside the semiconductor memory device;
• and
• an error correction circuit configured to generate second data as corrected data based on first data corresponding to the input data, the first data being received from the nonvolatile memory cell array, and a second set of parity bits corresponding to the first set of parity bits, the second set of parity bits being received from the nonvolatile memory cell array,
• wherein the semiconductor memory device is configured to use the second data to repair a defective cell included in the DRAM cell array.

A semiconductor memory device comprising:

• a memory cell array;
• a parity bit generator configured to generate a first set of parity bits having at least one bit based on first data received from outside the semiconductor memory device;
• an anti-fuse cell array including a plurality of anti-fuse cells configured to store the first data and the first set of parity bits, and to transfer second data corresponding to the first data, and a second set of parity bits corresponding to the first set of parity bits;
• and
• an error correction circuit configured to generate third data as corrected data based on the second data and the second set of parity bits,
• wherein the semiconductor memory device is configured to use the third data to select a spare cell of the memory cell array.