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US 9,436,539 B2Granted
Synchronized debug information generation
AssigneeInternational Business Machines Corporation
InventorsAjay K. Mahajan, Venkatesh Sainath, Vishwanatha Subbanna
Life of this patent
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Abstract
In an approach for determining a location of failure between interconnects/controller, a computer collects debug information simultaneously at a plurality of nodes coupled to an interconnect. Subsequent to collecting debug information, the computer analyzes the debug information collected simultaneously thereby determining which end of the interconnect caused the failure.
Claims5
A method for determining a location of failure between interconnects/controller, the method comprising:
- determining, by a first system controller coupled to a second system controller and a plurality of node controllers of a server computer, an error in the server computer, wherein the server computer includes a plurality of service processors configured in a hierarchical architecture;
- responsive to determining the error in the server computer, determining, by the first system controller, that a simultaneous dump should be performed by a plurality of both the second system controller and the plurality of node controllers;
- responsive to determining that the simultaneous dump should be performed, broadcasting, by the first system controller, an alert to the plurality of both the second system controller and the plurality of node controllers to perform a simultaneous dump;
- and
- receiving, by the first system controller, the simultaneous dump from the plurality of both the second system controller and the plurality of node controllers.
2 more elements
Dependencies are inferred from the claim text.