Techniques for managing the execution order of multiple nested tasks executing on a parallel processor
AssigneeNVIDIA Corporation
InventorLuke Durant
Life of this patent
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AssigneeNVIDIA Corporation
InventorLuke Durant
Estimating the term…
One embodiment of the present disclosure sets forth an enhanced way for GPUs to queue new computational tasks into a task metadata descriptor queue (TMDQ). Specifically, memory for context data is pre-allocated when a new TMDQ is created. A new TMDQ may be integrated with an existing TMDQ, where computational tasks within that TMDQ include task from each of the original TMDQs. A scheduling operation is executed on completion of each computational task in order to preserve sequential execution of tasks without the use of atomic locking operations. One advantage of the disclosed technique is that GPUs are enabled to queue computational tasks within TMDQs, and also create an arbitrary number of new TMDQs to any arbitrary nesting level, without intervention by the CPU. Processing efficiency is enhanced where the GPU does not wait while the CPU creates and queues tasks.
A computer-implemented method for processing a plurality of tasks being executed by a first group of threads and stored within a plurality of task metadata descriptor queues (TMDQs), the method comprising:
A subsystem for processing a plurality of tasks being executed by a first group of threads and stored within a plurality of task metadata descriptor queues (TMDQs), comprising:
A computing device, comprising:
Dependencies are inferred from the claim text.