System and method for executing sequential code using a group of threads and single-instruction, multiple-thread processor incorporating the same

A method of executing sequential code, comprising:

• creating a group of counterpart threads of said sequential code in a single instruction, multiple thread (SIMT) processor, one of said counterpart threads being a master thread, remaining ones of said counterpart threads being slave threads;
• executing certain instructions of said sequential code only in said master thread, corresponding instructions in said slave threads being predicated upon said certain instructions;
• and
• broadcasting branch conditions in said master thread to said slave threads,
• wherein lanes of said SIMT processor execute in lock-step.

A single-instruction, multiple-thread (SIMT) processor, comprising:

• lanes;
• local memories associated with corresponding ones of said lanes;
• shared memory device by said lanes;
• and
• a pipeline control unit configured to create a group of counterpart threads of said sequential code and cause said group to be executed in said lanes, one of said counterpart threads being a master thread, remaining ones of said counterpart threads being slave threads, said lanes configured to:
• execute certain instructions of said sequential code only in said master thread, corresponding instructions in said slave threads being predicated upon said certain instructions, and
• broadcast branch conditions in said master thread to said slave threads,
• wherein all of said lanes operate of said SIMT processor execute in lock-step.