Scheduling program instructions with a runner-up execution position
AssigneeArm Limited
InventorsRune Holm, Jr., David Hennah Mansell
Life of this patent
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AssigneeArm Limited
InventorsRune Holm, Jr., David Hennah Mansell
Estimating the term…
A single instruction multiple thread (SIMT) processor includes scheduling circuitry for calculating a next scheduled execution point for execution circuits which execute respective threads corresponding to a common program. In addition to calculating the next scheduled execution point, the scheduling circuitry determines a runner up execution point which would have been determined as the next scheduled execution point if the threads which actually correspond to the next scheduled execution point had been removed from consideration. This runner up execution point is used to identify points of re-convergence within the program flow and as part of the operation of a static branch predictor.
Apparatus for processing data comprising:
Apparatus for processing data comprising:
A method of processing data comprising the steps of:
Dependencies are inferred from the claim text.