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US 9,436,468 B2Granted
Technique for setting a vector mask
AssigneeIntel Corporation
InventorsRoger Espasa, Roger Gramunt
Life of this patent
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Abstract
A technique to generate a vector mask. In particular, at least one embodiment of the invention matches at least two instructions used in generating a vector mask and prevents at least one of the two instructions from executing if the correlation is found.
Claims20
A processor comprising:
- a first logic to detect a first decoded operation of a first instruction to store a vector mask value in a vector mask register;
- a second logic to identify a second decoded operation of a second instruction that is a vector instruction to generate the vector mask value;
- and
- a third logic to prevent the first decoded operation from being performed if the second decoded operation is identified;
- and
- a unit to perform the second decoded operation to generate the vector mask value and to store the generated vector mask value to the vector mask register.
3 more elements
A system comprising:
- a memory to store a first instruction and a second instruction, the first instruction to store a vector mask value in a vector mask register, the second instruction, which is a vector instruction, to generate the vector mask value;
- and
- a processor to store the vector mask value in the vector mask register while performing the second instruction, which is the vector instruction, when a destination register of the second instruction matches a source register of the first instruction, and to omit performing the first instruction.
A method comprising:
- detecting a first decoded operation of a first instruction to store a vector mask value in a vector mask register;
- identifying a second decoded operation of a second instruction, which is a vector instruction, to generate the vector mask value;
- preventing the first decoded operation from being performed if the second decoded operation is identified;
- and
- performing the second decoded operation to generate the vector mask value and to store the generated vector mask value to the vector mask register.
2 more elements
A processor comprising:
- an instruction queue to queue:
- a second decoded operation of a second vector instruction, wherein the second vector instruction if performed is to generate a vector mask value and is to store the generated vector mask value in a vector register;
- and
- a first decoded operation of a first instruction, wherein the first instruction if performed is to store the vector mask value from the vector register to a vector mask register;
- and
- a unit, when the first and second decoded operations are detected in the instruction queue, to store the vector mask value in the vector mask register without the vector mask value being stored in the vector register.
3 more elements
Dependencies are inferred from the claim text.