Instruction-issuance controlling device and instruction-issuance controlling method

A multithread processor comprising:

• an instruction execution unit;
• and
• an instruction-issuance controlling device,
• wherein the instruction-issuance controlling device includes:
• a resource management unit configured to manage stall information indicating whether or not each of threads in execution is in a stalled state;
• a thread selection unit configured to select a thread which is not in the stalled state among the threads in execution;
• and
• an instruction-issuance controlling unit configured to perform controlling so that simultaneously issuable instructions are issued from the selected thread to the instruction execution unit,
• wherein the resource management unit is configured to, for each of the threads in execution, (i) manage the number of stalled cycles which indicates the number of remaining cycles for the stalled state to determine whether or not the number of the stalled cycles is one or more, and (ii) determine that the thread is not in the stalled state and update the stall information if the number of the stalled cycles is 0.

A simultaneous multithreading (SMT) multithread processor by which a plurality of instruction groups are simultaneously issued to an instruction execution unit, the SMT multithread processor comprising

• an instruction-issuance controlling device including:
• a resource management unit configured to manage stall information indicating whether or not each of threads in execution is in a stalled state;
• a thread selection unit configured to select threads which are not in the stalled state from among the threads in execution;
• and
• an instruction grouping unit configured to perform controlling so that a plurality of instruction groups, each of which belongs to a corresponding one of the selected threads, are simultaneously issued to the instruction execution unit,
• wherein the resource management unit is configured to, for each of the threads in execution, (i) manage the number of stalled cycles which indicates the number of remaining cycles for the stalled state to determine whether or not the number of the stalled cycles is one or more, and (ii) determine that the thread is not in the stalled state and update the stall information if the number of the stalled cycles is 0.

An instruction-issuance controlling method for use in a multithread processor, comprising:

• managing stall information indicating whether or not each of threads in execution is in a stalled state;
• selecting a thread which is not in the stalled state from among the threads in execution;
• and
• performing controlling so that simultaneously issuable instructions are issued from among the selected thread,
• wherein the managing stall information comprises, for each of the threads in execution, (i) managing the number of stalled cycles which indicates the number of remaining cycles for the stalled state to determine whether or not the number of the stalled cycles is one or more, (ii) and determining that the thread is not in the stalled state and updating the stall information if the number of the stalled cycles is 0.