Technique for live analysis-based rematerialization to reduce register pressures and enhance parallelism
AssigneeNVIDIA Corporation
InventorsXiangyun Kong, Jian-Zhong Wang, Yuan Lin, Vinod Grover
Life of this patent
Estimating the term…
Loading patent…
AssigneeNVIDIA Corporation
InventorsXiangyun Kong, Jian-Zhong Wang, Yuan Lin, Vinod Grover
Estimating the term…
A device compiler and linker within a parallel processing unit (PPU) is configured to optimize program code of a co-processor enabled application by rematerializing a subset of live-in variables for a particular block in a control flow graph generated for that program code. The device compiler and linker identifies the block of the control flow graph that has the greatest number of live-in variables, then selects a subset of the live-in variables associated with the identified block for which rematerializing confers the greatest estimated profitability. The profitability of rematerializing a given subset of live-in variables is determined based on the number of live-in variables reduced, the cost of rematerialization, and the potential risk of rematerialization.
A computer-implemented method for optimizing program code that is capable of being compiled for execution on a parallel processing unit (PPU), the method comprising:
A non-transitory computer-readable medium storing program instructions that, when executed by a processing unit, cause the processing unit to optimize program code that is capable of being compiled for execution on a parallel processing unit (PPU) by performing the steps of:
A computing device configured to optimize program code that is capable of being compiled for execution on a parallel processing unit (PPU), including:
Dependencies are inferred from the claim text.