Systems and methods for hardware resource sharing

A non-transitory computer-readable medium comprising program instructions, the program instructions when executed by a processing element operable to:

• receive an executable, source graphical model configured to execute over a plurality of model steps, the executable, source graphical model including at least one subsystem including data paths, the data paths including a plurality of blocks;
• generate an in-memory representation of the executable, source graphical model, the in-memory representation including a portion that corresponds to the at least one subsystem, the portion of the in-memory representation including a plurality of functional components that correspond to the blocks of the data paths;
• search the portion of the in-memory representation corresponding to the at least one subsystem to identify a set of functional components that are functionally equivalent;
• modify the in-memory representation of the executable, source graphical model automatically, by a processing element, to create a modified in-memory representation, the program instructions to modify including program instructions to:
• replace the set of functional components that are functionally equivalent with a single shared component,
• configure the portion of the in-memory representation with conditional execution control,
• provide a counter, and
• connect the counter to the conditional execution control through one or more logic blocks to configure the portion of the in-memory representation to execute at determined ones of the plurality of model steps;
• and
• generate from the modified in-memory representation one or more of an executable validation graphical model, a report, source code, and a hardware description.

A non-transitory computer-readable medium comprising program instructions, the program instructions when executed by a processing element operable to:

• receive a source graphical model including execution semantics, the source graphical model executing over a plurality of time steps and including a subsystem including a plurality of data paths, the plurality of data paths having a data width;
• generate an in-memory representation of the source graphical model, the in-memory representation including a portion that corresponds to the subsystem;
• modify the in-memory representation of the source graphical model to create a modified in-memory representation, the modifying including:
• reducing the data width of at least one of the data paths;
• inserting at least one data unbuffer component into the portion of the in-memory representation,
• inserting at least one hardware demultiplexor component into the portion of the in-memory representation,
• connecting the at least one data unbuffer component and the at least one hardware demultiplexor component to the at least one of the data paths,
• configuring the portion of the in-memory representation with conditional execution control,
• providing a counter, and
• connecting the counter to the conditional execution control through control logic so that the portion of the in-memory representation executes at determined time steps;
• and
• generate from the modified in-memory representation one or more of an executable validation graphical model, a report, source code, and a hardware description.

An apparatus comprising:

• a memory storing an executable, source graphical model configured to execute over a plurality of model steps, the executable, source graphical model including at least one subsystem including data paths, the data paths including a plurality of blocks;
• a processor coupled to the memory, the processor configured to:
• generate an in-memory representation of the executable, source graphical model, the in-memory representation including a portion that corresponds to the at least one subsystem, the portion of the in-memory representation including a plurality of functional components that correspond to the blocks of the data paths;
• search the portion of the in-memory representation corresponding to the at least one subsystem to identify a set of functional components that are functionally equivalent;
• modify the in-memory representation of the executable, source graphical model automatically to create a modified in-memory representation, the modify including:
• replace the set of functional components that are functionally equivalent with a single shared component,
• configure the portion of the in-memory representation with conditional execution control,
• provide a counter, and
• connect the counter to the conditional execution control through one or more logic blocks to configure the portion of the in-memory representation to execute at determined ones of the plurality of model steps;
• and
• generate from the modified in-memory representation one or more of an executable validation graphical model, a report, source code, and a hardware description.