Checksum adder
AssigneeInternational Business Machines Corporation
InventorsJames R. Cuffney, John G. Rell, Jr., Eric M. Schwarz, Patrick M. West, Jr.
Life of this patent
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Abstract
Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.
Claims20
A computer system for executing multiple functions, the system comprising:
- a memory;
- and
- a processor, communicatively coupled to said memory, the computer system configured to perform a method comprising:
- driving, by the processor, a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition;
- and
- driving, by the processor, a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.
A computer implemented method for implementing multiple functions, the method comprising:
- driving, by a computer, a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition;
- and
- driving, by the computer, a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.
A computer program product for implementing multiple functions, the computer program product comprising:
- a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a signal, the program instructions readable by a processing circuit to cause the processing circuit to perform a method comprising:
- driving a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition;
- and
- driving a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition.
Dependencies are inferred from the claim text.