First-in first-out (FIFO) memory with multi-port functionality
AssigneeSTMicroelectronics International N.V.
InventorKapil Batra
Life of this patent
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Abstract
A memory may require a buffering mechanism in which data can be written and read at the same time. This requires a multi-port FIFO memory, which has multiple ports, thus providing simultaneous read & write operations. Multi-port memories have a large penalty on area. Hence, a technique is proposed for avoiding use of multi-port memories for designs which requires sequential read and write operations. In this technique multiple single-port memories are used to form a multi-port memory. This memory requires additional control logic but consumes significantly lower silicon area.
Claims18
A first-in first-out (FIFO) memory providing multi-port functionality, the FIFO memory comprising:
- a plurality of single-port memory structures, each single port memory structure having a plurality of addresses to read and write data thereto;
- an indexing block configured to store, for each data write operation, a unique memory identifier corresponding to a single-port memory structure in which the data write operation is performed;
- and
- an access controller configured to control operations in the single-port memory structures based on contents of the indexing block,
- wherein the access controller is configured to perform a plurality of write operations to the plurality of single-port memory structures in a single clock cycle,
- and
- wherein the access controller is further configured to continue at least one write operation of the plurality of write operations in the single clock cycle to a write address of a different single port memory structure of the plurality of single-port memory structures during the single clock cycle whenever there is a read and write operation request at a same time on one of the plurality of single-port memory structures.
A method of operating a plurality of single-port memory structures as a multi-port first-in first-out (FIFO) memory for sequential memory operations, each single-port memory structure having a plurality of addresses to read and write data thereto, the method comprising:
- maintaining a unique identifier corresponding to each of the single-port memory structure;
- for each of a plurality of data write operations to the FIFO memory in a single clock cycle:
- performing a “read operation active” check to find which of the plurality of single-port memory structures is free for the data write operations, and
- storing the unique identifier corresponding to the single-port memory structure in which a data write operation is done in an indexing block, wherein the indexing block stores K×N bits, where K bits are required for storing the unique identifier of a single-port memory structure and the multi-port FIFO memory has N locations;
- performing data read operations at a same time sequential with the data write operations based on the contents of the indexing block to ascertain the single-port memory structure which has to be read, wherein during the read operation a “read operation active” flag is enabled to indicate unavailability of the single-port memory structure for the data write operation;
- and
- continuing at least one data write operation of the plurality of data write operations in the single clock cycle to a write address of a different single-port memory structure of the plurality of single-port memory structures whenever there is a read and write operation request at a same time on one of the plurality of single-port memory structures during the single clock cycle.
A first-in first-out (FIFO) memory structure providing multi-port functionality for a FIFO queue, the FIFO memory structure comprising:
- a plurality of single-port memory structures, each single port memory structure having a plurality of addresses to read and write data thereto;
- an access controller configured to maintain pointer information for read and write operations in the plurality of single-port memory structures;
- and
- an indexing block configured to store a unique memory identifier corresponding to a single-port memory structure in which a data write operation is performed,
- wherein the access controller is configured to perform a plurality of write operations to the plurality of single-port memory structures in a single clock cycle,
- and
- wherein the access controller is further configured to continue at least one write operation of the plurality of write operations in the single clock cycle to a write address of a different single port memory structure of the plurality of single-port memory structures during the single clock cycle whenever there is a read and write operation request at a same time on one of the plurality of single-port memory structures.
Dependencies are inferred from the claim text.