Memory controller with on-chip linked list memory

A method, comprising:

• receiving, in a memory controller, data to be stored in a memory;
• managing, in the memory controller, a linked list using pointers retrieved from a free list, wherein the free list is implemented as part of the memory controller and contains a plurality of pointers that each point to locations in the memory that are unallocated,
• wherein managing the linked list includes assembling the linked list from pointers of the free list in response to receiving the data that is to be stored in the memory, wherein the data is a network packet, and wherein pointers of the linked list indicate addresses of where the network packet is to be stored in the memory;
• and
• storing, in a list memory that is an on-chip memory of the memory controller, the linked list,
• wherein storing the linked list includes storing a descriptor of the linked list in a queue that is implemented in an on-chip memory of the memory controller, wherein the descriptor includes a head pointer that references a first entry of the linked list, a tail pointer that references a final entry of the linked list and a pointer count that indicates a number of pointers in the linked list for the network packet, and wherein storing the descriptor includes storing a descriptor for network packets that ingressing and for network packets that are egressing,
• wherein receiving the network packet includes receiving the network packet in a network interface card that includes the memory controller;
• in response to a memory access request for a portion of the data referenced by a pointer in the linked list, traversing, by the memory controller, the linked list using the pointers to access the portion that is referenced by at least one of the pointers and modify the portion of data according to the memory access request.

A device, comprising:

• an ingress memory controller configured to assemble an ingress linked list of pointers for each network packet received from a network, wherein the ingress linked list of pointers includes pointers that are assigned to point to locations in a memory where successive portions of each network packet are to be stored once allocated;
• an egress memory controller configured to assemble an egress linked list of pointers for each network packet egressing the device to the network, wherein the egress linked list of pointers includes pointers that are assigned to point to locations in the memory where successive portions of each network packet are to be stored once allocated;
• a linked list memory connected to the egress memory controller and the ingress memory controller, wherein the egress memory controller and the ingress memory controller are configured to store the ingress linked list and the egress linked list respectively in the linked list memory, wherein the linked list memory is an on-chip memory of the device;
• a pointer memory connected to the ingress controller and the egress controller, wherein the egress memory controller and the ingress memory controller are configured to store a free list of pointers in the pointer memory, wherein the free list of pointers includes pointers to addresses in the memory that are unallocated, wherein the ingress memory controller and egress memory controller are configured to use pointers from the free list when assembling the ingress linked list and the egress linked list;
• and
• an egress descriptor memory connected to the egress memory controller and configured to store descriptors of linked lists for network packets egressing the device, wherein the device is part of a network interface card,
• wherein the ingress memory controller and the egress memory controller are configured to traverse the ingress linked list or the egress linked list, respectively, in response to a memory access request for a portion of each network packet referenced by the ingress linked list or the egress linked list and to modify the portion according to the memory access request.