Memory access alignment in a double data rate (‘DDR’) system

An apparatus for memory access alignment in a double data rate (‘DDR’) system, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the processor, cause the apparatus to carry out the steps of:

• executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module;
• executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module;
• and
• determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.