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US 9,436,245 B2Granted
Dynamically computing an electrical design point (EDP) for a multicore processor
AssigneeIntel Corporation
InventorsMalini K. Bhandaru, Eric J. Dehaemer, Jeremy J. Shrall
Life of this patent
Estimating the term…
Abstract
In one embodiment, a multicore processor includes a controller to dynamically limit a maximum permitted turbo mode frequency of its cores based on a core activity pattern of the cores and power consumption information of a unit power table. In one embodiment, the core activity pattern can indicate, for each core, an activity level and a logic unit state of the corresponding core. Further, the unit power table can be dynamically computed based on a temperature of the processor. Other embodiments are described and claimed.
Claims16
A processor comprising:
- a plurality of cores each to independently execute instructions, each of the plurality of cores to operate at an independent voltage and frequency;
- and
- a power controller coupled to the plurality of cores and including first logic to group the plurality of cores into a first group of cores corresponding to inactive cores, a second group of cores corresponding to cores to operate at or below a guaranteed maximum operating frequency, and a third group of cores corresponding to cores to request a turbo mode frequency, determine a power consumption for the first and second groups of cores, determine an available power budget for the third group of cores based on the determined power consumption for the first and second groups of cores, and perform an iterative search for a maximum permitted turbo mode frequency for the third group of cores based at least in part on information in a unit power table including a plurality of entries, each entry to associate a turbo mode frequency with a first power consumption level at which a core is to operate when first circuitry of the core is to not execute and a second power consumption level at which the core is to operate when the first circuitry is to execute.
A system comprising:
- a multicore processor including a plurality of cores each to independently execute instructions and to operate at an independent voltage and frequency, and a power control unit (PCU) to dynamically limit a maximum permitted turbo mode frequency of the plurality of cores based on a core activity pattern of the plurality of cores that indicates for each of the plurality of cores an activity level and a logic unit state of the corresponding core and power consumption information of a unit power table, wherein the PCU is to dynamically compute the power consumption information of the unit power table based on a temperature of the multicore processor, the unit power table including a plurality of entries, each entry to associate a turbo mode frequency with a first power consumption level at which a core is to operate when a first logic unit of the core is to not execute and a second power consumption level at which the core is to operate when the first logic unit is to execute.
A processor comprising:
- a plurality of cores each to independently execute instructions, each of the plurality of cores to operate at an independent voltage and frequency;
- and
- a power controller coupled to the plurality of cores and including a first logic to group the plurality of cores into a first group of cores corresponding to inactive cores, a second group of cores corresponding to cores to operate at or below a guaranteed maximum operating frequency, and a third group of cores corresponding to cores to request a turbo mode frequency and determine a power consumption for the first and second groups of cores, a second logic to determine an available power budget for the third group of cores based on the determined power consumption for the first and second groups of cores, and a third logic to search for a maximum permitted turbo mode frequency for the third group of cores, wherein the power controller includes a unit power table having a plurality of entries, each entry to associate a turbo mode frequency with a first power consumption level at which a core is to operate when first circuitry of the core is to not execute and a second power consumption level at which the core is to operate when the first circuitry is to execute.
Dependencies are inferred from the claim text.