Gated state machine circuitry having three clock 2 enable states
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.
Claims9
Controller circuitry comprising:
- A. state machine circuitry having a command 0 input, a command 1 input, a frame marker input, a scan clock input, a test enable input, a clock 2 enable output, a parallel scan enable output, and a serial scan enable output, in response to signals on the command 0 input, the command 1 input, and the frame marker input, and clock signal cycles on the scan clock input, the state machine circuitry having:
- i. a first state producing an enable signal on the clock 2 enable output of one clock signal cycle;
- ii. a second state producing enable signals on the clock 2 enable output of two clock signal cycles;
- and
- iii. a third state producing enable signals on the clock 2 enable output of three clock signal cycles;
- B. first gate circuitry having a first input connected to clock 2 enable output, a second input connected to the scan clock input, and a clock 2 output;
- and
- C. second gate circuitry having a first input connected to the scan clock input, a second input connected to the test enable input, and a clock 1 output.
Dependencies are inferred from the claim text.