Interposer capture shift update cell between functional and test data

An integrated circuit interposer comprising:

• A. a substrate having a first side and an opposed second side;
• B. first functional input pads formed on the first side of the substrate;
• C. first functional output pads formed on the second side of the substrate and coupled to the first functional input pads;
• D. second functional input pads formed on the second side of the substrate;
• E. second functional output pads formed on the first side of the substrate and coupled to the second functional input pads;
• F. a test data input pad, a test clock input pad, a test mode select input pad, and a test data output pad formed on the first side of the substrate;
• G. a test access port controller, formed on the substrate, coupled to the test clock input pad and the test mode select input pad, and having a control output bus;
• and
• H. boundary register circuitry formed on the substrate, the boundary register circuitry including input boundary scan cells, each input boundary scan cell including a functional input coupled to a first functional input pad, a functional output coupled to a first functional output pad, a test data input coupled to the test data input pad, a test data output coupled to the test data output pad, and a control input coupled to the control output bus of the test access port controller, each input boundary scan cell including:
• i. a capture shift update cell that is coupled between the functional input and the functional output, the capture shift update cell also being coupled between the test data input and the test data output, and the capture shift update cell also being coupled to the control input, and
• ii. multiplexer circuitry that is coupled between the functional input and output and is also coupled between the capture shift update cell and the functional output.