Out-of-band (OOB) detection circuit for serial/deserializer (SERDES)

An out-of-band (OOB) detection circuit, comprising:

• a positive input node;
• a negative input node;
• a resistive circuit coupled between a first supply node and ground, the resistive circuit including a first node outputting a positive threshold value and a second node outputting a negative threshold value;
• an initial gain stage coupled to the positive input node and the negative input node
• a first comparator coupled to compare a differential output of the initial gain stage to the positive threshold value
• a second comparator coupled to compare the differential output of the initial gain stage to the negative threshold value
• first and second gain stages coupled to outputs of the first and second comparators, respectively;
• an OR gate coupled to outputs of the first and second gain stages;
• and
• a detection filter coupled to an output of the OR gate, the detection filter comprising:
• a first NOR gate having a first input coupled to a clock signal;
• a second NOR gate having a first input coupled to the output of the OR gate;
• a third NOR gate having a first input coupled to the output of the OR gate;
• a fourth NOR gate having a first input coupled to an inverse of the clock signal;
• wherein an output of the first NOR gate is coupled to a second input of the second NOR gate, and an output of the second NOR gate is coupled to a second input of the first NOR gate;
• wherein an output of the third NOR gate is coupled to a second input of the fourth NOR gate, and an output of the fourth NOR gate is coupled to a second input of the third NOR gate;
• a first multiplexer having a first input coupled to the output of the first NOR gate and driven by the clock signal;
• a second multiplexer having a first input coupled to the output of the fourth NOR gate and driven by the inverse of the clock signal;
• a first inverter having an input coupled to an output of the first multiplexer;
• a second inverter having an input coupled to an output of the first inverter and an output coupled to a second input of the first multiplexer;
• a third inverter having an input coupled to an output of the second multiplexer;
• a fourth inverter having an input coupled to an output of the third inverter and an output coupled to a second input of the second multiplexer;
• and
• a third multiplexer coupled having a first input coupled to the output of the second inverter and a second input coupled to the output of the fourth inverter.

An apparatus, comprising:

• an out-of-band (OOB) detection circuit coupled to a positive input node and a negative input node, the OOB detection circuit including an output providing either a present signal or an absent signal in response to a differential voltage at the positive and negative input nodes;
• and
• a detection filter, coupled to the output of the OOB detection circuit, the detection filter comprising:
• a first NOR gate having a first input coupled to a clock signal;
• a second NOR gate having a first input coupled to the output of the OR gate;
• a third NOR gate having a first input coupled to the output of the OR gate;
• a fourth NOR gate having a first input coupled to an inverse of the clock signal;
• wherein an output of the first NOR gate is coupled to a second input of the second NOR gate, and an output of the second NOR gate is coupled to a second input of the first NOR gate;
• wherein an output of the third NOR gate is coupled to a second input of the fourth NOR gate, and an output of the fourth NOR gate is coupled to a second input of the third NOR gate;
• a first multiplexer having a first input coupled to the output of the first NOR gate and driven by the clock signal;
• a second multiplexer having a first input coupled to the output of the fourth NOR gate and driven by the inverse of the clock signal;
• a first inverter having an input coupled to an output of the first multiplexer;
• a second inverter having an input coupled to an output of the first inverter and an output coupled to a second input of the first multiplexer;
• a third inverter having an input coupled to an output of the second multiplexer;
• a fourth inverter having an input coupled to an output of the third inverter and an output coupled to a second input of the second multiplexer;
• and
• a third multiplexer coupled having a first input coupled to the output of the second inverter and a second input coupled to the output of the fourth inverter.