Vertical memory devices and methods of manufacturing the same

A method of manufacturing a vertical memory device, the method comprising:

• forming a first semiconductor structure on a substrate including a first region and a second region, the first semiconductor structure being in the second region;
• forming a plurality of sacrificial layers and a plurality of insulating interlayers on the substrate alternately and repeatedly;
• partially removing the sacrificial layers and the insulating interlayers to form a mold structure in the first region and the second region and a protection layer pattern in the second region simultaneously, the protection layer pattern covering the first semiconductor structure;
• forming a plurality of holes through the sacrificial layers and the insulating interlayers to expose a top surface of the substrate in the first region;
• forming a charge storage structure and a channel filling each of the holes;
• partially removing the sacrificial layers to form a plurality of gaps exposing a sidewall of each charge storage structure;
• and
• forming a gate electrode to fill each of the gaps.

A vertical memory device, comprising:

• a substrate including a first region, a second region and a third region;
• a first semiconductor structure in the second region;
• a second semiconductor structure in the third region;
• a charge storage structure on a sidewall of ones of a plurality of channels in the first region;
• a plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in a first direction that is substantially perpendicular to a top surface of the substrate;
• a plurality of remaining sacrificial layer patterns that are at a same level as the plurality of gate electrodes, respectively, wherein a lowermost one of the plurality of remaining sacrificial layer patterns substantially covers the second semiconductor;
• and
• a protection layer pattern substantially covering the first semiconductor structure, the protection layer pattern having a thickness that is substantially similar to a thickness of a lowermost gate electrode.