Multi-chip package
AssigneeSK hynix Inc.
InventorDong-Beom Lee
Life of this patent
Estimating the term…
Abstract
A multi-chip package includes first and second semiconductor chips that are sequentially stacked, each of the first and second semiconductor chips including an operation block for an internal operation, third and fourth semiconductor chips that are sequentially stacked over the second semiconductor chip and rotated 180 degrees in a horizontal direction with respect to the first and second semiconductor chips, each of the third and fourth semiconductor chips including an operation block, and through chip vias for transmitting predetermined signals between the operation blocks of the first to fourth semiconductor chips.
Claims14
A multi-chip package, comprising:
- a master chip including transmission/reception circuits suitable for transmitting/receiving a predetermined data;
- a first slave region that includes data transmission/reception blocks suitable for transmitting/receiving data to/from the master chip through first chip vias and is vertically stacked over the master chip;
- and
- a second slave region that includes data transmission/reception blocks suitable for transmitting/receiving the predetermined data to/from the master through second chip vias and is vertically stacked over the first slave region, wherein the data transmission/reception blocks of the first slave region and the first chip vias are arranged over a first portion of the master chip, and the data transmission/reception blocks of the second slave region and the second chip vias are arranged over a second portion of the master chip, which is opposite to the first portion.
A multi-chip package, comprising:
- a master chip;
- first to fourth slave chips sequentially and vertically stacked over the master chip;
- and
- through chip vias for transmitting a predetermined signal between the master chip and the first to fourth slave chips,
- wherein each of the first to fourth slave chips includes a signal transmission circuit block for exchanging the predetermined signal with the master chip through one of the through chip vias,
- wherein the signal transmission circuit blocks coupled to the same through chip via are disposed to overlap with each other, and the signal transmission circuit blocks coupled to different through chip vias are disposed not to overlap with each other, and
- wherein the signal transmission circuit blocks of the first and second slave chips and the through chip vias coupled thereto are arranged over a first portion of the master chip, and the signal transmission circuit blocks of the third and fourth slave chips and the through chip vias coupled thereto are arranged over a second portion of the master chip, which is opposite to the first portion.
Dependencies are inferred from the claim text.