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US 9,431,322 B2Granted
Semiconductor device having stacked chips
AssigneeKabushiki Kaisha Toshiba
InventorMasaru Koyanagi
Life of this patent
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Abstract
According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip.
Claims13
A semiconductor device comprising:
- chips each of which has at least first and second vias through each chip from a front surface of the chip to a back surface of the chip, the vias enabling transmission of at least first and second address signals, and the chips being electrically connected to each other through the first and second vias and stacked;
- and
- a first selection circuit which is provided in each chip, and includes a wiring configuration that selects the chips by selecting one of the first and second address signals;
- wherein the first selection circuit comprises:
- first and second wiring layers which are connected to the first and second vias in each chip, respectively;
- and
- a third wiring layer which is selectively connected to the first and second wiring layers.
4 more elements
A semiconductor device comprising:
- chips each of which has at least first and second vias through each chip from a front surface of the chip to a back surface of the chip, the vias enabling transmission of at least first and second address signals, and the chips being electrically connected to each other through the first and second vias and being stacked;
- a first selection circuit which is provided in each chip and selects a chip based on at least the first and second address signals;
- and
- a second selection circuit which selects a first chip from the chips based on a first selection signal supplied from the first selection circuit and an externally supplied address signal.
1 more element
Dependencies are inferred from the claim text.