Semiconductor device and manufacturing method of the same
AssigneeToyoda Gosei Co., Ltd.
InventorsNariaki Tanaka, Tohru Oka
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Abstract
There is provided a manufacturing method of a semiconductor device having an N-type semiconductor layer on a P-type semiconductor layer. The manufacturing method comprises: a dry etching process of performing dry etching to go through the N-type semiconductor layer in a thickness direction and make the plane in the thickness direction of the P-type semiconductor layer exposed; and a annealing process of annealing the P-type semiconductor layer in an atmosphere containing oxygen, after the dry etching process. This manufacturing method improves the electrical properties of the P-type semiconductor layer.
Claims14
A manufacturing method of a semiconductor device having an N-type semiconductor layer on a P-type semiconductor layer, the manufacturing method comprising:
- a dry etching process of performing dry etching to go through the N-type semiconductor layer in a thickness direction in order to expose a surface of the P-type semiconductor layer;
- and
- an annealing process of annealing the P-type semiconductor layer in an atmosphere comprising oxygen, after the dry etching process,
- wherein a width of the P-type semiconductor layer exposed by the dry etching process is not less than 1% of a half pitch of the semiconductor device.
A method of manufacturing a semiconductor device, comprising:
- forming a first N-type semiconductor layer on substrate;
- forming a P-type semiconductor layer on the first N-type semiconductor layer;
- forming a second N-type semiconductor layer on the P-type semiconductor layer;
- performing a dry etching of the second N-type semiconductor layer to form a plurality of recesses in the N-type semiconductor layer, the surface of the P-type semiconductor layer being exposed through a first recess of the plurality of recesses;
- and
- after the performing of the drying etching, annealing the P-type semiconductor layer in an atmosphere comprising oxygen,
- wherein a width of the surface of the P-type semiconductor layer exposed by the dry etching is not less than 1% of a half pitch of the semiconductor device, the half pitch comprising a distance between a center axis of a first recess and a center axis of a second recess of the plurality of recesses.
Dependencies are inferred from the claim text.