Memory-network processor with programmable optimizations

A method for operating a processor, the method comprising:

• receiving a multi-part instruction, wherein the multi-part instruction includes a plurality of fields;
• performing an arithmetic operation for a first thread of sub-instructions dependent on a first field of the plurality of fields and storing a result of the first arithmetic operation in a register;
• generating a given address of a plurality of addresses dependent upon a respective field of the plurality of fields and using the given address to access one or more input operands for an execution unit for a second thread of sub-instructions;
• and
• using the result of the first arithmetic operation stored in the register to access one or more input operands for the execution unit for a sub-instruction in the first thread of sub-instructions in a subsequent multi-part instruction.

A system, comprising:

• a plurality of processors;
• and
• a plurality of dynamically configurable communication elements;
• wherein the plurality of processors and the plurality of dynamically configurable communication elements are coupled together in an interspersed arrangement;
• wherein a given processor of the plurality of processors is configured to:
• receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields;
• perform an arithmetic operation for a first thread of sub-instructions dependent upon a given field of the plurality of fields and store a result of the first arithmetic operation in a register;
• generate a plurality of addresses dependent upon a subset of the plurality of fields, wherein the given processor is configured to use the plurality of addresses to access one or more input operands for an execution unit for a second thread of sub-instructions, and
• use the result of the first arithmetic operation stored in the register to access one or more input operands for the execution unit for a sub-instruction in the first thread of sub-instructions in a subsequent multi-part instruction.