Silicon-based rib-waveguide modulator and fabrication method thereof

A fabrication method of an electro-optic device, comprising:

• forming a first silicon-on-insulator (SOI) wafer that comprises a first silicon substrate, a first buried oxide (BOX) layer, and a first top silicon layer which is formed over the first BOX layer;
• performing a first ion-implantation process to form a first doped region in the first top silicon layer, the first doped region being at least partially doped with dopants of a first conducting type;
• performing a first thermal treat process to form a first thin dielectric layer over the first top silicon layer;
• preparing a second SOI wafer that comprises a second silicon substrate, a second BOX layer, and a second top silicon layer which is formed over the second BOX layer;
• performing a wafer bonding process to combine the first SOI wafer and the second SOI wafer, with the second top silicon layer bonded face-to-face to the thin dielectric layer;
• performing a grinding process and a first dry-etching process to remove the second silicon substrate of the second SOI wafer, using the second BOX layer as a stop layer for the first dry-etching process;
• performing a second dry-etching process to remove the second BOX layer, using the second top silicon layer as a stop layer for the second dry-etching process;
• performing a second ion-implantation process to form a second doped region in the second top silicon layer, the second doped region being at least partially doped with dopants of a second conducting type;
• performing a third dry-etching process to form a rib waveguide on the second top silicon layer;
• and
• performing a passivation process and a metallization process to form a first electric contact on the first top silicon layer and a second electric contact formed on the second top silicon layer.

A fabrication method of an electro-optic device, comprising:

• preparing a first silicon-on-insulator (SOI) wafer that comprises a first silicon substrate, a first buried oxide (BOX) layer, and a first top silicon layer which is formed over the first BOX layer;
• performing a first thermal treat process to form a first thin dielectric layer over the first top silicon layer;
• preparing a second SOI wafer that comprises a second silicon substrate, a second BOX layer, and a second top silicon layer which is formed over the second BOX layer;
• performing a wafer bonding process to combine the first SOI wafer and the second SOI wafer, with the second top silicon layer bonded face-to-face to the thin dielectric layer;
• performing a grinding process and a first dry-etching process to remove the second silicon substrate of the second SOI wafer, using the second BOX layer as a stop layer for the first dry-etching process;
• performing a second dry-etching process to remove the second BOX layer, using the second top silicon layer as a stop layer for the second dry-etching process;
• performing a third dry-etching process to form a rib waveguide on the second top silicon layer, wherein a window region of the second top silicon layer is etched down to the thin dielectric layer;
• performing a first ion-implantation process to implant, through the window region, impurities of a first type into the first top silicon layer;
• performing a third thermal treat process to cause lateral diffusion of the impurities of the first type to form a first conducting-type region in the first top silicon layer;
• performing a second ion-implantation process to form a second conducting-type region in the second top silicon layer with impurities of a second type;
• and
• performing a passivation process and a metallization process to form a first electric contact on the first top silicon layer and a second electric contact formed on the second top silicon layer.

An electro-optic device, comprising:

• a silicon-based rib-waveguide modulator comprising:
• a first top silicon region which is at least partially doped to exhibit electrical conductivity of a first type;
• a thick dielectric layer, having a thickness approximately identical to a thickness of the first top silicon region, the thick dielectric layer filling a space of a plane of the first top silicon region;
• a second top silicon region which is at least partially doped to exhibit electrical conductivity of a second type, the second top silicon region at least in part directly over the first top silicon region;
• a thin dielectric gate layer disposed between the first top silicon region and the second top silicon region, the thin dielectric gate layer comprising a first side in contact with the first top silicon region and a second side in contact with the second top silicon region;
• a rib waveguide formed on the second top silicon region;
• a first electric contact formed on the first top silicon region;
• and
• a second electric contact formed on the second top silicon region,
• wherein, when electric signals are applied on the first and second electric contacts, free carriers accumulate, deplete, or invert within the first and second top silicon regions on the first and second sides of the thin dielectric gate layer simultaneously and a refractive index of the rib waveguide confining optical field is modulated.

A fabrication method of an electro-optic device, comprising:

• preparing a first silicon-on-insulator (SOI) wafer that comprises a first silicon substrate, a first buried oxide (BOX) layer, and a first top silicon layer which is formed over the first BOX layer;
• performing a first ion-implantation process to form a first doped region in the first top silicon layer, the first doped region at least partially doped to exhibit electrical conductivity of a first type;
• performing a first dry-etching process to etch parts of the first top silicon layer down to the first BOX layer to form a first top silicon region with at least a portion of the first doped region preserved;
• performing a thick dielectric deposition process to form a thick dielectric layer with a thickness sufficient to entirely cover the first top silicon region;
• performing a chemical-mechanical polishing (CMP) process to planarize the thick dielectric layer to remove a part of the thick dielectric layer that is above the first top silicon region;
• performing a first thermal treat process to form a first thin dielectric layer over the first top silicon region;
• preparing a second SOI wafer that comprises a second silicon substrate, a second BOX layer, and a second top silicon region which is formed over the second BOX layer;
• performing a wafer bonding process to combine the first SOI wafer and the second SOI wafer with the second top silicon layer bonded face-to-face to the thin dielectric layer;
• performing a grinding process and a second dry-etching process to remove the second silicon substrate of the second SOI wafer, using the second BOX layer as a stop layer for the second dry-etching process;
• performing a third dry-etching process to remove the second BOX layer, using the second top silicon region as a stop layer for the third dry-etching process;
• performing a second ion-implantation process to form a second doped region in the second top silicon region, the second doped region at least partially doped to exhibit electrical conductivity of a second type, the second doped region at least in part directly over the first doped region;
• performing a fourth dry-etch process to form the rib waveguide on the second top silicon region;
• and
• performing a passivation process and a metallization process to form a first electric contact on the first top silicon region and a second electric contact formed on the second top silicon region.

A Mach-Zehnder interferometer, comprising:

• an input optical waveguide splitter comprising a first arm, a second arm, and an input waveguide part optically coupled to the first arm and the second arm which are positioned in parallel;
• and
• an output optical waveguide combiner comprising an output waveguide part optically coupled to the first arm and the second arm of the input optical waveguide splitter,
• wherein the first arm of the input optical waveguide splitter comprises a first electro-optic phase modulator, the first electro-optic phase modulator comprising:
• a first top silicon layer which is at least partially doped to exhibit electrical conductivity of a first type;
• a second top silicon layer which is at least partially doped to exhibit electrical conductivity of a second type, a doped region of the second top silicon layer being at least in part directly over a doped region of the first top silicon layer;
• a thin dielectric gate layer disposed between the first top silicon layer and the second top silicon layer;
• a rib waveguide formed on the second top silicon layer;
• a first electric contact formed on the first top silicon layer;
• and
• a second electric contact formed on the second top silicon layer,
• wherein, when electric signals are applied on the first and second electric contacts, free carriers accumulate, deplete, or invert within the first and second top silicon layers on the first and second sides of the thin dielectric gate layer simultaneously and a refractive index of the rib waveguide confining optical field is modulated.