Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems

An adaptive clock distribution system for delaying a clock signal provided to a clocked circuit, comprising:

• a means for measuring a timing margin between a clock signal period of a clock signal and a path delay of a data input signal in a selected tunable delay path among a plurality of tunable delay paths each having a delay timing based on a critical-path delay timing in a clocked circuit, based on a programmable delay path input;
• a means for detecting a voltage droop event on a voltage droop output indicating a voltage droop of a power supply supplying power to the clocked circuit, based on the measured timing margin between the clock signal period and the path delay of the data input signal;
• a means for:
• receiving a first delayed clock signal comprised of a delayed clock signal of the clock signal on a second clock signal input;
• reducing a frequency of the first delayed clock signal to provide a reduced frequency delayed clock signal;
• selectively providing the reduced frequency delayed clock signal on a second clock output to the clocked circuit if the voltage droop output indicates the voltage droop event;
• and
• selectively providing the first delayed clock signal on the second clock output to the clocked circuit if the voltage droop output does not indicate the voltage droop event;
• and
• a means for providing the programmable delay path input to the means for measuring the timing margin to select the selected tunable delay path among the plurality of tunable delay paths in the means for measuring the timing margin that produces a lower path timing margin of the clock signal period and the path delay of the data input signal in the means for measuring the timing margin without the voltage droop event being generated by the means for detecting the voltage droop event.

A method of adaptively distributing a delayed clock signal to a clocked circuit, comprising:

• receiving a clock signal;
• measuring a timing margin of a clock signal period of the clock signal and a path delay of a data input signal in a selected tunable delay path among the plurality of tunable delay paths each having a delay timing based on a critical-path delay timing in a clocked circuit, based on a programmable delay path input;
• detecting a voltage droop event of a power supply supplying power to a clocked circuit;
• generating a voltage droop output indicating the voltage droop event based on the measured timing margin of the clock signal period and the path delay of the data input signal;
• selectively providing a reduced frequency delayed clock signal of the clock signal to the clocked circuit if the voltage droop output indicates the voltage droop event;
• selectively providing a first delayed clock signal on a second clock output to the clocked circuit if the voltage droop output does not indicate the voltage droop event;
• calibrating the plurality of tunable delay paths based on the programmable delay path input, based on the selected tunable delay path among the plurality of tunable delay paths that produces a lower path timing margin of the clock signal period and the path delay of the data input signal without the voltage droop event being generated on the voltage droop output;
• and
• generating the programmable delay path input to select the selected tunable delay path among the plurality of tunable delay paths during operation of the clocked circuit, based on the calibrating of the plurality of tunable delay paths.