Level-sensitive two-phase single-wire latch controllers without contention
AssigneeAltera Corporation
InventorDana How
Life of this patent
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Abstract
Systems and methods are described for a contention-free single-wire latch controller that includes first and second bidirectional signal pins (e.g., the L and R pins in the FIGS), a latch enable output pin (or signal), E, and a decision element (such as a NAND or a NOR gate). A first driving transistor may be coupled between the first bidirectional signal pin and a power rail. A second driving transistor may be coupled between the second bidirectional signal pin and the power rail. A first half-latch may be coupled to the first bidirectional signal pin. A second half-latch may be coupled to the second bidirectional signal pin.
Claims18
A contention-free controller for a data latch, the controller comprising:
- first and second bidirectional signal pins;
- a decision element;
- a first driving transistor coupled between the first bidirectional signal pin and a power rail;
- a second driving transistor coupled between the second bidirectional signal pin and the power rail;
- a first tri-stateable half-latch coupled to the first bidirectional signal pin;
- and
- a second tri-stateable half-latch coupled to the second bidirectional signal pin,
- wherein the decision element is a gate comprising an input for the first bidirectional signal pin and an input for one of the second bidirectional signal pin and an inverted version of the second bidirectional signal pin.
A contention-free controller for a data latch, the controller comprising:
- a plurality of bidirectional signal pins;
- a latch enable output pin;
- a decision element;
- a plurality of tri-stateable half-latches coupled to the plurality of bidirectional signal pins,
- wherein the decision element is a gate comprising an input for a first bidirectional signal pin of the plurality of bidirectional signal pins and an input for one of a second bidirectional signal pin of the plurality of bidirectional signal pins and an inverted version of the second bidirectional signal pin of the plurality of bidirectional signal pins.
Dependencies are inferred from the claim text.