RC oscillator based on delay-free comparator
AssigneeQUALCOMM Incorporated
InventorsLe Wang, Arash Mehrabi
Life of this patent
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Abstract
Cancelling a delay in a comparator of an RC oscillator configured to generate a clock pulse, including: selectively coupling a plurality of current sources to a first capacitor, a second capacitor, and a resistor, wherein the plurality of current source charge and discharge the first capacitor and the second capacitor, and charge the resistor; charging the first capacitor at a higher rate during a first phase of the clock pulse than a second phase of the clock pulse, and charging the second capacitor at a higher rate during a third phase of the clock pulse than a fourth phase of the clock pulse; and generating the clock pulse by enabling the comparator to compare a voltage on the first or second capacitor with a voltage on the resistor.
Claims20
A method for cancelling a delay in a comparator of an RC oscillator configured to generate a clock pulse, the method comprising:
- selectively coupling a plurality of current sources to a first capacitor, a second capacitor, and a resistor,
- wherein the plurality of current sources charge and discharge the first capacitor and the second capacitor, and charge the resistor;
- charging the first capacitor at a higher rate during a first phase of the clock pulse than a second phase of the clock pulse, and charging the second capacitor at a higher rate during a third phase of the clock pulse than a fourth phase of the clock pulse;
- and
- generating the clock pulse by enabling the comparator to compare a voltage on the first or second capacitor with a voltage on the resistor.
The method of 1, wherein the first capacitor is charged at 50% higher rate during the first phase and the second capacitor is charged at 50% higher rate during the third phase.
An RC oscillator which generates a clock pulse, the RC oscillator comprising:
- a comparator delay cancellation circuit comprising:
- a resistor and a pair of capacitors including a first capacitor and a second capacitor;
- a plurality of current sources configured to charge and discharge the pair of capacitors and the resistor,
- wherein the first capacitor is charged during first and second phases of the clock pulse and is discharged during third and fourth phases of the clock pulse, and the second capacitor is charged during the third and fourth phases of the clock pulse and is discharged during the first and second phases of the clock pulse,
- wherein the first capacitor is charged at a same rate during the first phase as the second phase, and the second capacitor is charged at a higher rate during the third phase than the fourth phase;
- a plurality of switches configured to selectively couple the plurality of current sources to the pair of capacitors and the resistor;
- a comparator having a first input and a second input, the comparator configured to generate the clock pulse by comparing a voltage on the first or second capacitor with a voltage on the resistor.
An apparatus to generate a clock pulse, the apparatus comprising:
- means for comparing two voltages having a first input and a second input;
- means for canceling delay in the means for comparing two voltages comprising:
- means for charging and discharging a first capacitor and a second capacitor,
- wherein the means for charging and discharging charges the first capacitor at a higher rate during a first phase of the clock than a second phase of the clock pulse, and charges the second capacitor at a higher rate during a third phase of the clock pulse than a fourth phase of the clock pulse;
- means for selectively coupling the means for charging and discharging to the pair of capacitors and a resistor,
- wherein the means for comparing two voltages generates the clock pulse by comparing a voltage on the first or second capacitor with a voltage on the resistor.
Dependencies are inferred from the claim text.