Methods and circuit structures for mitigating voltage stresses on printed circuit board (PCB) in high voltage devices

A method for mitigating voltage stresses on a printed circuit board (PCB), comprising:

• forming a multi-terminal condenser structure on a multi-layered PCB and the multi-terminal condenser structure is configured to by-pass electric fields of an alternating current (AC) voltage applied to the multi-terminal condenser structure, which powers circuitries external to the multi-terminal condenser structure, wherein the multi-terminal condenser structure itself is free from having PCB components mounted thereon, wherein:
• the multi-terminal condenser structure is formed by overlapping a plurality of conductive traces disposed between board layers of the multi-layered PCB,
• a corresponding dielectric layer is disposed between the plurality of overlapping conductive traces of the board layers, wherein the plurality of overlapping conductive traces comprise:
• at least a first terminal a second terminal, a third terminal and a fourth terminal, wherein the first terminal and the third terminal are disposed on the first layer of the multi-layered PCB, and the second terminal and the fourth terminal are disposed on the bottom layer of the multi-layered PCB;
• wherein the first terminal and the second terminal are connected to a ground point as the only return ground point for AC currents, and the third terminal and the fourth terminal are connected to the AC voltage;
• and
• mitigating voltage stresses on the PCB utilizing the multi-terminal condenser structure to by-pass the AC currents from the applied AC voltage to the ground point.