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AssigneeSemiconductor Manufacturing International (Shanghai) Corporation
InventorsGuoHao Cao, Guangli Yang, Yang Zhou, GangNing Wang
Estimating the term…
A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers, selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes remains after the selective etch, and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes.
A method of fabricating a semiconductor device, comprising:
A method of fabricating a semiconductor device, comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
Drawings are temporarily unavailable. Open the PDF at USPTO
Insulated-gate field-effect transistors [IGFET]: having multiple independently-addressable gate electrodes influencing the same channel
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
Of conductive parts of the interconnections: local interconnections
Inorganic electric semiconductor devices
About 6 years 11 months of term left · ends 14 Sep 2033 (estimated)
This application claims priority under 35 U.S.C. §119 to Chinese Patent Application No. 201210483778.3, filed on Nov. 23, 2012 and entitled “SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME”, which is incorporated herein by reference in its entirety.
The present invention relates to semiconductors, and more particularly, to a semiconductor device and method of fabricating the same.
Further miniaturization of semiconductor devices and integration of ICs (Integrated Circuits) can increase performance of the semiconductor devices and ICs. However, the miniaturization of semiconductor devices poses scaling challenges, particularly in the fabrication of the semiconductor devices. The scaling challenges will be briefly described with reference to FIG. 1, which shows a cross-sectional view of a metal oxide semiconductor (MOS) device in the related art.
The following detailed description of some embodiments of the inventive concept will be more clearly understood when read in conjunction with the appended drawings. It should be understood, however, that the embodiments are not limited to the arrangements and instrumentalities as shown. In the drawings, like numerals are used to indicate like elements throughout. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, in view of the accompanying drawings and the foregoing technical field and background.
For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring aspects of the illustrated embodiments. Additionally, the elements in the drawings may not be drawn to scale.
FIG. 1 is a cross-section view of a metal oxide semiconductor (MOS) device in the related art.
The detailed description set forth below with reference to the appended drawings is intended to be a description of some embodiments of the inventive concept. It is to be understood that the same or equivalent functions may be accomplished by different embodiments.
The terms “first”, “second”, and other such terms in the description and the claims, if present, are used to distinguish between similar elements. The terms do not necessarily prescribe a particular sequence or chronological order. It is to be understood that the terms as used are interchangeable under appropriate circumstances such that the embodiments described herein can be used in sequences other than those illustrated or otherwise described. Furthermore, the terms “comprise,” “include,” “have” and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises, includes, or has a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Below, a semiconductor device and method of fabricating the semiconductor device according to an embodiment of the inventive concept will be described with reference to FIGS. 2-6.