Memory cell array
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShi-Wei Chang, Hong-Chen Cheng, Chien-Chi Tien, Li-Chun Tien, Kuo-Hua Pan, Jhon-Jhy Liaw
Life of this patent
Estimating the term…
Abstract
A semiconductor memory cell array is disclosed that includes a memory cell unit. The memory cell unit includes an active region, a first transistor, a second transistor, a gate structure, and an interconnect. The first transistor and the second transistor are formed on the active region. The gate structure is formed on the active region and between the first transistor and the second transistor. The interconnect connects the gate structure and at least one of sources of the first transistor and the second transistor to a power line.
Claims22
A semiconductor memory cell array comprising:
- a memory cell unit comprising:
- an active region;
- a first transistor formed on the active region;
- a second transistor formed on the active region;
- a gate structure formed on the active region and between the first transistor and the second transistor, and configured to be biased by a power line to electrically isolate the first transistor from the second transistor;
- and
- an interconnect connecting the gate structure and at least one of sources of the first transistor and the second transistor to the power line.
A semiconductor memory cell array comprising:
- a plurality of memory cells comprising:
- an active region;
- a first gate, a second gate, and a third gate, wherein the first gate, the second gate, and the third gate are formed on the active region, and the second gate is disposed between the first gate and the third gate;
- a first metal line formed on the active region, wherein the first metal line is disposed between the first gate and the second gate;
- and
- an interconnect in contact with the second gate and the first metal line and connecting the second gate and the first metal line to a power line.
A method comprising:
- forming a first gate, a second gate, and a third gate on an active region, wherein the second gate is disposed between the first gate and the third gate;
- forming a first metal line on the active region and between the first gate and the second gate;
- and
- forming an interconnect in at least one memory cell, wherein the interconnect is in contact with the second gate and the first metal line, and connects the second gate and the first metal line to a power line.
Dependencies are inferred from the claim text.