Semiconductor constructions

A semiconductor construction, comprising:

• a semiconductor substrate having a plurality of active area locations, and having isolation regions adjacent the active area locations and separating the active area locations from one another;
• neighboring active areas being spaced from one another by a first distance;
• floating gates over the active areas, a first floating gate being over one active area and a second floating gate being over the neighboring active area that is closest to said first floating gate, and being closest to said first floating gate of any floating gates that are over said neighboring active area;
• the first and second floating gates being spaced from one another by a second distance which is at least 10 Å greater than the first distance;
• the first and second floating gates each consisting of a rectangular shape and comprising a single material;
• the rectangular floating gates having completely planar horizontal lower surfaces directly contacting gate dielectric material and having completely planar horizontal upper surfaces in opposing relation to the lower surfaces;
• the rectangular floating gates having a width of from 10 nm to 35 nm and having vertical sidewalls that join to the upper and lower surfaces at 90° corners;
• insulative spacers consisting of a rectangular shape partially covering opposing vertical sidewalls of the rectangular floating gates, wherein material of the insulative spacers does not extend lower than the gate dielectric and has planar upper surfaces that are coplanar with planar upper surfaces of the isolation regions;
• source/drain regions within the active areas, the source/drain regions not being between first and second floating gates;
• insulative material extending over the first and second floating gates;
• the upper surfaces of the first and second floating gates directly contacting the insulative material;
• and
• control gate material over the insulative material.

A semiconductor construction, comprising:

• a semiconductor substrate having a plurality of active area locations, and having isolation regions adjacent the active area locations and separating the active area locations from one another;
• neighboring active areas being spaced from one another by a first distance;
• floating gates over the active areas, a first floating gate being over one active area and a second floating gate being over the neighboring active area that is closest to said first floating gate, and being closest to said first floating gate of any floating gates that are over said neighboring active area;
• the first and second floating gates being spaced from one another by a second distance which is at least 25% greater than the first distance;
• the first and second floating gates consisting of a rectangular shape and comprising a single material;
• the rectangular floating gates having completely planar horizontal lower surfaces directly contacting gate dielectric material and having completely planar horizontal upper surfaces in opposing relation to the lower surfaces;
• the rectangular floating gates having a width of from 10 nm to 35 nm and having vertical sidewalls that join to the upper and lower surfaces at 90° corners;
• insulative spacers consisting of a rectangular shape partially covering opposing vertical sidewalls of the rectangular floating gates, wherein material of the insulative spacers does not extend lower than the gate dielectric and has planar upper surfaces that are coplanar with planar upper surfaces of the isolation regions;
• source/drain regions within the active areas, the source/drain regions not being between first and second floating gates;
• insulative material extending over the floating gates;
• the upper surfaces of the first and second floating gates directly contacting the insulative material;
• and
• control gate material over the insulative material.

A semiconductor construction, comprising:

• a semiconductor substrate having a plurality of active areas, and having isolation regions adjacent the active areas and separating the active areas from one another;
• floating gates over the active areas, the floating gates having a width of from 10 nm to 35 nm which is less than a width of the active areas;
• the floating gates consisting of a rectangular shape, adjacent floating gates being separated from one another by gaps along a first axis;
• insulative spacers partially covering opposing vertical sidewalls of the rectangular floating gates, the insulative spacers consisting of a rectangular shape with planar upper surfaces that are coplanar with planar upper surfaces of the isolation regions;
• source/drain regions within the active areas;
• paired source/drain regions being associated with individual floating gates, with the individual source/drain regions of paired source/drain regions being on opposing sides of the individual floating gate associated with the paired source/drain regions;
• the paired source/drain regions associated with an individual floating gate being along a second axis relative to the floating gate which is substantially orthogonal to the first axis;
• insulative material extending over the floating gates and within the gaps, the upper surfaces of the floating gates directly contacting the insulative material;
• and
• control gate material extending over the insulative material and within the gaps.