Half-integer frequency dividers that support 50% duty cycle signal generation

A frequency divider, comprising:

• a multi-modulus divider comprising a cascaded chain of div2/3 cells, which is responsive to a multi-bit modulus control signal;
• a phase control circuit configured support half-integer frequency division by said multi-modulus divider by providing an input terminal of said multi-modulus divider with a periodically phase-flipped input signal having a first frequency;
• and
• a duty-cycle adjustment circuit configured to adjust a non-uniform duty cycle of a divider output signal generated at an output terminal of said multi-modulus divider upward to a 50% duty cycle, said duty-cycle adjustment circuit comprising a D-type flip-flop having a clock terminal responsive to the divider output signal.

A fractional-N frequency divider, comprising:

• a half-integer frequency divider, comprising:
• a multi-modulus divider comprising a cascaded chain of div2/3 cells, which is responsive to a multi-bit modulus control signal;
• and
• a phase control circuit configured support half-integer frequency division by said multi-modulus divider by providing an input terminal of said multi-modulus divider with a periodically phase-flipped input signal having a first frequency;
• and
• a duty-cycle adjustment circuit configured to generate an output signal with a 50% duty cycle in response to a periodic signal generated by said half-integer frequency divider having a less than 50% duty cycle, said duty-cycle adjustment circuit comprising a D-type flip-flop having a clock terminal responsive to the periodic signal generated by said half-integer frequency divider;
• wherein said phase control circuit comprises a multiplexer having a select terminal responsive to a first output signal generated by the D-type flip-flop and an output terminal electrically coupled to the input terminal of said multi-modulus divider.

A frequency divider, comprising:

• a half-integer frequency divider, comprising:
• a multi-modulus divider comprising a cascaded chain of divider cells, which is responsive to a multi-bit modulus control signal;
• and
• a phase control circuit configured support half-integer frequency division by said multi-modulus divider by providing an input terminal of said multi-modulus divider with an input signal having a first frequency;
• and
• a duty-cycle adjustment circuit responsive to a periodic output signal generated by said half-integer frequency divider, said duty-cycle adjustment circuit configured to perform at least a dual function of generating a signal having an increased duty cycle relative to the periodic output signal and driving said phase control circuit with a control signal that synchronizes timing of the input signal.

A fractional-N frequency divider, comprising:

• a multi-modulus divider comprising a cascaded chain of div2/3 cells, which is responsive to a multi-bit modulus control signal;
• and
• a phase control circuit configured to provide an input terminal of said multi-modulus divider with a periodically phase-flipped input signal having a first frequency, said phase control circuit comprising a multiplexer having first and second input terminals, a select terminal and an output terminal at which the periodically phase-flipped input signal is generated;
• and
• a duty-cycle adjustment circuit configured to:
• (i) generate an output signal having a second duty cycle in response to a periodic signal having a first duty cycle, which is generated by said half-integer frequency divider, and (ii) provide the select terminal of the multiplexer with a control signal that synchronizes the periodic phase-flipping of the input signal, where the second duty cycle is greater than the first duty cycle, which is less than 50%.