Vertical nanowire transistor for input/output structure

A system for protecting a circuit from an electrostatic discharge (ESD) voltage, the system comprising:

• an input terminal for receiving an input signal;
• a semiconductor substrate including a first well region and a second well region, wherein the first well region is of a first conductivity type, and the second well region is of a second conductivity type;
• an ESD protection circuit configured to receive the input signal from the input terminal, the ESD protection circuit including:
• a first vertical nanowire field effect transistor (FET), wherein a first PN junction is formed between the first well region and a source or drain region of the first vertical nanowire FET, and
• a second vertical nanowire FET, wherein a second PN junction is formed between the second well region and a source or drain region of the second vertical nanowire FET;
• and
• an output terminal configured to receive the input signal from the ESD protection circuit.

A system for protecting a circuit from an electrostatic discharge (ESD) voltage, the system comprising:

• an input terminal for receiving an input signal;
• an ESD protection circuit configured to receive the input signal from the input terminal, the ESD protection circuit including one or more vertical nanowire field effect transistors (FETs), wherein each of the one or more vertical nanowire FETs includes:
• a well of a first conductivity type that is formed in a semiconductor substrate,
• a nanowire having i) a drain region at a first end of the nanowire, and ii) a source region at a second end of the nanowire that is opposite the first end, the drain region further including a portion formed in the well, wherein the drain region and the source region are of a second conductivity type such that a PN junction is formed between the well and the portion of the drain region formed in the well, and
• a gate region surrounding a portion of the nanowire, wherein the gate region is separated from the source region by a first distance, the separation of the gate region and the source region providing a resistance in series between the source region and the drain region;
• and
• an output terminal configured to receive the input signal from the ESD protection circuit, wherein an ESD-induced voltage in the input signal is attenuated by the resistance and the PN junction.