Self-adaptive multi-modulus dividers containing div2/3 cells therein

An integrated circuit device, comprising:

• a multi-modulus divider comprising a cascaded chain of div2/3 cells configured to support a chain length control operation that precludes generation of an intermediate divisor in response to a change in value of a chain length control byte during an update time interval and freezes one or more of the div2/3 cells not participating in a divide-by-N operation in a power saving mode of operation, where N is a positive integer greater than one, said cascaded chain comprising a plurality of div2/3 cells having respective stage number control (SNC) terminals that receive respective SNC signals, which are each derived exclusively from respective Boolean combinations of a plurality of bits of the chain length control byte.

An integrated circuit device, comprising:

• a multi-modulus divider comprising a cascaded chain of div2/3 cells configured to support a chain length control operation that precludes generation of any intermediate divisor in response to a change in value of a chain length control byte during an update time interval when all modulus input signals (MODin) associated with active ones of the div2/3 cells participating in a divide-by-N operation are in a first logic state, where N is a positive integer greater than one;
• each of a plurality of the div2/3 cells in the cascaded chain has a first terminal responsive to a respective bit of the chain length control byte and a second terminal responsive to a respective bit of a multi-bit stage number control (SNC) byte;
• and each of a plurality of bits of the SNC byte is derived exclusively from a respective Boolean combination of a plurality of bits of the chain length control byte.