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US 9,077,348 B1Granted
Fractional clock generator
AssigneeMaxim Integrated Products, Inc.
InventorHaichen Liu
Life of this patent
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Abstract
Various embodiments of the invention allow the generation of an output clock signal that comprises a frequency that is a fractional frequency of an input clock signal and is adjusted with respect to an input signal. A fractional clock generator that has high performance output, low power consumption, small area, and good jitter performance is presented.
Claims20
A fractional clock generator comprising:
- a phase splitter that generates phase signals from an input clock signal having a first frequency;
- a phase generator coupled to receive the phase signals and output a plurality of clock signals of the first frequency, each of the plurality of clock signals comprises has a different phase angle;
- a phase multiplexer coupled to the phase generator, the phase multiplexer selects a predetermined sequence of the plurality of clock signals in response to receiving a feedback signal, the phase multiplexer configured to generate an output clock signal of a second frequency that can be selected lower and higher than the first frequency;
- and
- a selection circuit coupled to the phase multiplexer, the selection circuit comprises a state machine circuit that receives the output clock signal at its input, generates a one-hot signal, and generates the feedback signal that controls the phase multiplexer, the state machine circuit comprising a plurality of flip-flops coupled to each other in a loop configuration such that a data output of each flip-flop is coupled to a data input of a preceding flip-flop.
2 more elements
A method to generate a fractional clock signal, the method comprising:
- splitting a phase of an input clock signal having an input frequency to generate phase signals;
- generating from the phase signals a plurality of clock signals having the input frequency, each of the plurality of clock signals comprises a phase angle different from at least one other of the plurality of clock signals;
- selecting a sequence of the plurality of clock signals in response to receiving a feedback signal;
- generating an output clock signal comprising an output frequency that can be selected lower and higher than the input clock signal and an output phase angle;
- and
- generating the feedback signal and a one-hot signal using a state machine circuit that receives the output clock signal from a multiplexer, wherein the different phase angles vary the period of the output clock signal with respect to the input clock signal such that the output frequency is different from the input frequency, and wherein the state machine circuit comprises a plurality of flip-flops coupled to each other in a loop configuration such that a data output of each flip-flop is coupled to a data input of a preceding flip-flop.
3 more elements
Dependencies are inferred from the claim text.