Method for tuning the effective work function of a gate structure in a semiconductor device

A method for tuning a first effective work function of a first gate structure in a first semiconductor device of a first type and tuning a second effective work function of a second gate structure in a second semiconductor device of a second type, the first and second semiconductor devices being part of an integrated circuit, the first and second gate structures comprising a metal layer and a high-k dielectric layer separating the metal layer from an active layer of the semiconductor devices, the method comprising:

• providing a first interconnect structure of the integrated circuit on top of the first gate structure, the first interconnect structure comprising a first layer stack with at least a first pre-metal dielectric layer having a first metal filled connecting via connected to the first gate structure through the first pre-metal dielectric layer, and the first interconnect structure having a first upper exposed metal portion;
• providing a second interconnect structure of the integrated circuit on top of the second gate structure, the second interconnect structure comprising a second layer stack with at least a second pre-metal dielectric layer having a second metal filled connecting via connected to the second gate structure through the second pre-metal dielectric layer, and the second interconnect structure having a second upper exposed metal portion;
• and
• thereafter, exposing at least part of the first and second upper exposed metal portions to a plasma under predetermined exposure conditions, to tune the first and second effective work functions of the first and second gate structures, wherein exposing at least part of the first upper exposed metal portion to a plasma is performed independently from exposing at least part of the second upper exposed metal portion to a plasma.

A method for tuning a first effective work function of a first gate structure in a first semiconductor device of a first type and tuning a second effective work function of a second gate structure in a second semiconductor device of a second type, the first and second semiconductor devices being part of an integrated circuit, the first and second gate structures comprising a metal layer and a high-k dielectric layer separating the metal layer from an active layer of the semiconductor devices, the method comprising:

• providing a first interconnect structure of the integrated circuit on top of the first gate structure, the first interconnect structure comprising a first layer stack with at least a first pre-metal dielectric layer having a first metal filled connecting via connected to the first gate structure through the first pre-metal dielectric layer, and the first interconnect structure having a first upper exposed metal portion;
• providing a second interconnect structure of the integrated circuit on top of the second gate structure, the second interconnect structure comprising a second layer stack with at least a second pre-metal dielectric layer having a second metal filled connecting via connected to the second gate structure through the second pre-metal dielectric layer, and the second interconnect structure having a second upper exposed metal portion;
• and
• thereafter, exposing at least part of the first and second upper exposed metal portions to a plasma under predetermined exposure conditions, to tune the first and second effective work functions of the first and second gate structures, wherein exposing at least part of the first and second upper exposed metal portions is performed with a single plasma.