US 9,070,786 B2Granted

Methods for forming transistors

AssigneeFreescale Semiconductor, Inc.

InventorVishal P. Trivedi

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Abstract

A hybrid transistor is produced to have a substrate with a first (e.g., P type) well region and a second (e.g., N type) well region with an NP or PN junction therebetween. A MOS portion of the hybrid transistor has an (e.g., N type) source region in the first well region and a gate conductor overlying and insulated from the well regions. A drain or anode (D/A) portion in the second well region collects current from the source region, and includes a bipolar transistor having an (e.g., N+) emitter region, a (e.g., P type) base region and a (e.g., N type) collector region laterally separated from the junction. Different LDMOS-like or IGBT-like properties are obtained depending on whether the current is extracted from the hybrid transistor via the bipolar transistor base or emitter or both. The bipolar transistor is desirably a vertical hetero-junction transistor.

Claims20

Dependent claims

A method for forming a transistor comprising:

providing a substrate having therein a first well region of a first conductivity type and a second well region of a second, opposite conductivity type, extending substantially to a first surface of the substrate, the first and second well regions forming an NP or PN junction therebetween, and wherein the first and the second well regions have therein an MOS-portion and the second well region has therein a drain or anode (D/A) portion;
forming in the MOS-portion, a gate conductor overlying and insulated from the first surface at least over the first well region and having a first lateral end adapted to substantially locate a first edge of a subsequently formed source region within the first well region and a second lateral end extending at least to the NP and PN junction;
protecting the MOS-portion while a bipolar transistor is subsequently formed in the D/A portion in the second well region;
forming the bipolar transistor in the second well region, wherein the bipolar transistor comprises an emitter region of the second conductivity type, an intrinsic base region of the first conductivity type communicating with the emitter region, and a collector region of the second conductivity type communicating with the intrinsic base region;
protecting the D/A portion and, in either order, forming the source region of the second conductivity type in the first well region and having the first edge laterally proximate the first lateral end of the gate conductor, and forming a well contact region of the first conductivity type in the first well region;
and
forming multiple conductive contacts communicating respectively with the source region, the gate conductor, the intrinsic base region of the bipolar transistor and the emitter region of the bipolar transistor.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/505,831Filed 3 Oct 2014 · division
Priority: 27 Jul 2012
Published: US 2015/0056767 A126 Feb 2015
Granted: 30 Jun 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/0109
Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00,…
H10D 84/401
Characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by…
H10D
Inorganic electric semiconductor devices

Family

Application13/560,533Parent of this division · filed 27 Jul 2012
US 2015/0056767 A1Pre-grant publication · published 26 Feb 2015
US 8,912,569 B2Parent of this division
US 2014/0027817 A1Published application
US 9,070,786 B2This patent

From the US filing history. Foreign family members aren’t listed.