Metal oxide TFT with improved temperature stability

A metal oxide thin film transistor comprising:

• a substrate;
• a gate supported by the substrate;
• a layer of gate dielectric covering at least a portion of the gate;
• a metal oxide semiconductor channel positioned on the layer of gate dielectric in overlying relationship to the gate, the metal oxide semiconductor channel having a conduction band with a first energy level;
• metal source/drain contacts positioned on the metal oxide semiconductor channel on opposite sides of the gate;
• and
• a layer of passivation material covering at least a portion of the metal oxide semiconductor channel between the source/drain contacts, the passivation material having a conduction band with a second energy level, the second energy level being equal to, or less than 0.5 eV above the first energy level, such that a barrier between the metal oxide semiconductor channel and the passivation layer is reduced allowing carriers to be drained off into the passivation layer.

A method of fabricating a metal oxide thin film transistor with improved temperature stability comprising, not necessarily in the order listed, the steps of:

• providing a substrate and forming a gate with a layer of gate dielectric covering at least a portion of the gate;
• depositing a metal oxide semiconductor layer on the gate dielectric opposite the gate, the metal oxide semiconductor layer having a conduction band with a first energy level;
• positioning spaced apart source and drain contacts on the metal oxide semiconductor layer and on opposite sides of the gate, the source and drain contacts defining a channel area in the metal oxide semiconductor layer between the spaced apart source and drain contacts and in substantial alignment with the gate;
• and
• positioning a layer of passivation material on the metal oxide semiconductor channel area, the passivation material having a conduction band with a second energy level, the second energy level being equal to, or less than 0.5 eV above the first energy level, such that a barrier between the metal oxide semiconductor channel and the passivation layer is reduced allowing carriers to be drained off into the passivation layer.