Test structure for semiconductor process and method for monitoring semiconductor process

A method of monitoring a semiconductor process, comprising:

• providing a semiconductor substrate with a gate structure;
• forming at least a test structure, comprising:
• forming a first doped region in the semiconductor substrate;
• forming a second doped region in the semiconductor substrate;
• forming an inter-layer dielectric (ILD) layer on the semiconductor substrate, wherein the ILD layer covers the gate structure;
• and
• directly forming a conductive layer on the ILD layer, wherein the conductive layer partially overlaps the first doped region and partially overlaps the second doped region, the conductive layer is laterally spaced apart from the gate structure and is in a floating state, the conductive layer overlaps the semiconductor substrate between the first doped region and the second doped region, and only the semiconductor substrate is disposed between the first doped region and the second doped region;
• applying a voltage signal to the test structure;
• and
• measuring a breakdown voltage (Vbd) between the first doped region and the second doped region.